Article

Congestion prediction in floorplanning

Authors:

Chiu-wing Sham,

Evangeline F. Y. YoungAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 1107 - 1110

https://doi.org/10.1145/1120725.1120835

Published: 18 January 2005 Publication History

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Abstract

Routability optimization has become the major concern in floorplanning. In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, interconnect has become a dominant factor to the overall performance of a circuit. Routability prediction is thus very important in the floorplanning stage. In this paper, we propose a new congestion model to predict the congestion after detailed routing which is not confined to the assumption of shortest Manhattan distance routes. We have compared our new models and some existing models with the actual congestion measures obtained by global routing some placement results (using the Capo placer [3]) with a publicly available maze router [2]. Results show that our models can make significant improvement in estimation accuracy over the other models.

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Cited By

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Zhou ZChahal SHo TIvanov A(2019)Supervised-Learning Congestion Predictor For Routability-Driven Global Routing2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT.2019.8742060(1-4)Online publication date: Apr-2019
https://doi.org/10.1109/VLSI-DAT.2019.8742060
Li WKim JChong J(2012)A novel congestion estimation model and congestion aware floorplan for 3D ICs2012 International Conference on Innovation Management and Technology Research10.1109/ICIMTR.2012.6236388(199-204)Online publication date: May-2012
https://doi.org/10.1109/ICIMTR.2012.6236388
Meister TLienig JThomke G(2011)Interface optimization for improved routability in chip-package-board co-designProceedings of the System Level Interconnect Prediction Workshop10.5555/2134224.2134234(1-8)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.5555/2134224.2134234
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Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominant factor of the overall performance of a circuit. In order to optimize ...

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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Zhou ZChahal SHo TIvanov A(2019)Supervised-Learning Congestion Predictor For Routability-Driven Global Routing2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT.2019.8742060(1-4)Online publication date: Apr-2019
https://doi.org/10.1109/VLSI-DAT.2019.8742060
Li WKim JChong J(2012)A novel congestion estimation model and congestion aware floorplan for 3D ICs2012 International Conference on Innovation Management and Technology Research10.1109/ICIMTR.2012.6236388(199-204)Online publication date: May-2012
https://doi.org/10.1109/ICIMTR.2012.6236388
Meister TLienig JThomke G(2011)Interface optimization for improved routability in chip-package-board co-designProceedings of the System Level Interconnect Prediction Workshop10.5555/2134224.2134234(1-8)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.5555/2134224.2134234
Meister TLienig JThomke G(2011)Interface optimization for improved routability in chip-package-board co-designProceedings of the International Workshop on System Level Interconnect Prediction10.1109/SLIP.2011.6135430(1-8)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1109/SLIP.2011.6135430
Sham CYoung ELu J(2009)Congestion prediction in early stages of physical designACM Transactions on Design Automation of Electronic Systems10.1145/1455229.145524114:1(1-18)Online publication date: 23-Jan-2009
https://dl.acm.org/doi/10.1145/1455229.1455241
Saeedi MZamani MJahanian A(2007)Evaluation, prediction and reduction of routing congestionMicroelectronics Journal10.1016/j.mejo.2007.07.12238:8-9(942-958)Online publication date: Aug-2007
https://doi.org/10.1016/j.mejo.2007.07.122

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Congestion-driven floorplanning with module reshaping

Fast floorplanning for effective prediction and construction

Congestion prediction in early stages

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Congestion-driven floorplanning with module reshaping

Fast floorplanning for effective prediction and construction

Congestion prediction in early stages

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