Article

An improved P-admissible floorplan representation based on Corner Block List

Authors:

Renshen Wang,

Sheqin Dong,

Xianlong HongAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 1115 - 1118

https://doi.org/10.1145/1120725.1120837

Published: 18 January 2005 Publication History

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Abstract

The Corner Block List representation (CBL) introduced in 2000 is an efficient and effective model for floorplanning and placement while still having some limitations such as redundancy and incompleteness. In this paper, we present an auxiliary 3-Route Model to eliminate the redundancy and insert empty rooms to resolve the incompleteness. Finally we attain a P-admissible representation ECBL(2) which has higher performances than the original CBL and the count of its solution space is O((2n)!2⁶ⁿ/n!n⁴).

References

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Lebedev BLebedev OLebedeva EKostyuk A(2017)VLSI Planning Based on the Ant Colony MethodProceedings of the Second International Scientific Conference “Intelligent Information Technologies for Industry” (IITI’17)10.1007/978-3-319-68321-8_40(388-397)Online publication date: 30-Sep-2017
https://doi.org/10.1007/978-3-319-68321-8_40
Renshen Wang Sheqin Dong Xianlong Hong (2005)Buffer space planning for long interconnections based on corner block list48th Midwest Symposium on Circuits and Systems, 2005.10.1109/MWSCAS.2005.1594293(1083-1086 Vol. 2)Online publication date: 2005
https://doi.org/10.1109/MWSCAS.2005.1594293

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Corner block list: an effective and efficient topological representation of non-slicing floorplan
ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

In this paper, a corner block list -- a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement. Given a corner block list, it takes only linear time to construct ...
An optimum placement search algorithm based on extended corner block list

A non-slicing approach, Corner Block List (CBL), has been presented recently. Since CBL only can represent floorplans without empty rooms, the algorithm based on CBL cannot get the optimum placement. In this paper, an extended corner block list. ECBL_λ, ...
VLSI floorplanning with boundary constraints based on corner block list
ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

In floorplanning of typical VLSI design, some modules are required to satisfy some placement constraints in the final packing. Boudary Constraint is one kind of those placement constraints to pack some modules along one of the four sides: on the left, ...

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ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Lebedev BLebedev OLebedeva EKostyuk A(2017)VLSI Planning Based on the Ant Colony MethodProceedings of the Second International Scientific Conference “Intelligent Information Technologies for Industry” (IITI’17)10.1007/978-3-319-68321-8_40(388-397)Online publication date: 30-Sep-2017
https://doi.org/10.1007/978-3-319-68321-8_40
Renshen Wang Sheqin Dong Xianlong Hong (2005)Buffer space planning for long interconnections based on corner block list48th Midwest Symposium on Circuits and Systems, 2005.10.1109/MWSCAS.2005.1594293(1083-1086 Vol. 2)Online publication date: 2005
https://doi.org/10.1109/MWSCAS.2005.1594293

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Corner block list: an effective and efficient topological representation of non-slicing floorplan

An optimum placement search algorithm based on extended corner block list

VLSI floorplanning with boundary constraints based on corner block list

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Corner block list: an effective and efficient topological representation of non-slicing floorplan

An optimum placement search algorithm based on extended corner block list

VLSI floorplanning with boundary constraints based on corner block list

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