Article

Variation tolerant buffered clock network synthesis with cross links

Authors:

David Z. PanAuthors Info & Claims

ISPD '06: Proceedings of the 2006 international symposium on Physical design

Pages 157 - 164

https://doi.org/10.1145/1123008.1123038

Published: 09 April 2006 Publication History

Abstract

Clock network synthesis is a key step in the ultra deep sub-micron (UDSM) VLSI Designs. Most existing clock network synthesis algorithms are designed for nominal operating condition, which are insufficient to address the growing problem of process, voltage and temperature (PVT) fluctuations. Link based clock networks have been suggested as a possible way of reducing skew variability [1-3]. However, [1,2] deal with only unbuffered clock networks, making them impractical. In [3], the problem of constructing a link based buffered clock network has been addressed . But [3] requires special kind of tunable buffers, which might consume more area/power and might not be available for all designs. Also, [3] uses SPICE for tuning the locations of internal nodes and buffer delays, thereby making it slow even for clock networks with a few hundred sinks. In this paper, we propose a unified algorithm for synthesizing a variation tolerant, balanced buffered clock network with cross links. Our approach can make use of ordinary buffers and does not require SPICE for clock network synthesis. SPICE based Monte Carlo simulations show that our methodology results in a buffered clock network with 50% reduction in skew variability with minimal increase in wire-length, buffer area and CPU time.

References

[1]

A. Rajaram, J. Hu, and R. Mahapatra, "Reducing clock skew variability via cross links," in Proceedings of the ACM/IEEE DAC, San Diego, CA, June 2004, pages 18--23.

Digital Library

[2]

A. Rajaram, D. Z. Pan, and J. Hu, "Improved Algorithms for Link-Based Non-Tree Clock Networks for Skew Variability Reduction," in Proceedings of the ISPD, San Francisco, CA, April 2005, pages 55--62.

Digital Library

[3]

G. Venkataraman, N. Jayakumar, J. Hu, P. Li, S. Khatri, A. Rajaram, P. McGuinness, and C. Alpert, "Practical Techniques for Minimizing Skew and Its Variation in Buffered Clock Networks," in Proc. of the ICCAD, San Jose, CA, pages 592-596, November 2005.

Digital Library

[4]

E. G. Friedman, "Clock distribution networks in synchronous digital integrated circuits," in Proceedings of the IEEE, vol. 89, no.5, pp.665--692, May 2001.

[5]

R. Saleh, S. Z. Hussain, S. Rochel, and D. Overhauser, "Clock skew verification in the presence of IR-drop in the power distribution network," in IEEE Transactions on CAD, vol.19, no.6, pp.635--644, June 2000.

Digital Library

[6]

W.-C. D. Lam, C.-K. Koh, and C.-W. A. Tsao, "Power supply noise suppression via clock skew scheduling," in Proceedings of the IEEE ISQED, San Jose, CA, March 2002, pp. 355--360.

Digital Library

[7]

R.-S. Tsay, "Exact zero skew," in Proceedings of the IEEE/ACM ICCAD, Santa Clara, CA, November 1991, pp. 336--339.

[8]

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wire-length," in IEEE Transactions on CS-ADSP, vol.39, no.11, pp.799--814, November 1992.

[9]

Y. P. Chen, and D.F. Wong, "An algorithm for zero-skew clock tree routing with buffer insertion," in Proceedings of the ED & TC, Pairs, France, March 1996, pp. 230--236.

Digital Library

[10]

S. Pullela, N. Menezes, and L. T. Pillage, "Low power IC clock tree design," in Proceedings of the CICC, May 1995, pp.263--266.

[11]

J. Chung and C.K. Cheng, "Optimal Buffered Clock Tree Synthesis," in IEEE ASIC conference, Austin, TX, Sept. 1994, pp. 130--133.

[12]

A. Vittal, and M. Marek-Sadowska, "Low-power buffered clock tree design," in IEEE Transactions on CAD, vol. 16, no. 9, pp. 965--975, Sept. 1997.

Digital Library

[13]

G. E. Tellez, and M. Sarrafzadeh, "Minimal buffer insertion in clock trees with skew and slew rate constraints" in IEEE Transactions of CAD, vol. 16, no.4, pp.333--342, April 1997.

Digital Library

[14]

A. D. Mehta, Y. P. Chen, N. Menezes, D. F. Wong, and L. T. Pilegg, "Clustering and load balancing for buffered clock tree synthesis" in Proceedings of the ICCD, Austin, Tx, October 1997, pp. 217--223.

Digital Library

[15]

J. Tai. Yan, C. W. Wu, K. P. Lin, Y. C. Lee, and T. Y. Wang, "Iterative convergence of optimal wire sizing and available buffer insertion for zero skew clock tree optimization" in Proceedings of Asia-Pacific Conference, December 2004, pp.529--532.

[16]

J. L. Tsai, T. H. Chen, and C. C. P. Chen, "Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing" in IEEE Transactions of CAD, vol. 23, no. 4, pp.565--572, April 2004.

Digital Library

[17]

R. Chaturvedi, and J. Hu, "Buffered clock tree for high quality IC design" in Proceedings of the ISQED, March 2004. pp. 381--386.

Digital Library

[18]

K. Wang, and M. Marek-Sadowska, "Clock network sizing via sequential linear programming with time-domain analysis" in Proceedings of the ISPD, Monterey, CA, April 2003, pp. 182--189.

Digital Library

[19]

R. Puri, D. S. Kung, and A. D. Drumm, "Fast and accurate wire delay estimation for physical synthesis of large ASICs" in Proceedings of the GLSVLSI, New York, NY, April 2002, pp. 30--36.

Digital Library

[20]

S. R. Nassif, "Modeling and analysis of manufacturing variations," in Proceedings of the IEEE CICC, San Diego, CA, May 2001, pp. 223--228.

Cited By

Chong AHong TIan KIzzat MHao LChau C(2022)Clock Optimization Techniques2022 IEEE 5th International Conference on Electronics Technology (ICET)10.1109/ICET55676.2022.9823968(321-326)Online publication date: 13-May-2022
https://doi.org/10.1109/ICET55676.2022.9823968
Madhuri GSelvakumar JKrishna K(2022)Performance Analysis on Skew Optimized Clock Tree Synthesis2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)10.1109/ICERECT56837.2022.10059632(01-06)Online publication date: 26-Dec-2022
https://doi.org/10.1109/ICERECT56837.2022.10059632
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889756
Show More Cited By

Index Terms

Variation tolerant buffered clock network synthesis with cross links
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

ISPD '06: Proceedings of the 2006 international symposium on Physical design

April 2006

232 pages

ISBN:1595932992

DOI:10.1145/1123008

General Chair:
Lou Scheffer
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Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 April 2006

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April 9 - 12, 2006

California, San Jose, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Chong AHong TIan KIzzat MHao LChau C(2022)Clock Optimization Techniques2022 IEEE 5th International Conference on Electronics Technology (ICET)10.1109/ICET55676.2022.9823968(321-326)Online publication date: 13-May-2022
https://doi.org/10.1109/ICET55676.2022.9823968
Madhuri GSelvakumar JKrishna K(2022)Performance Analysis on Skew Optimized Clock Tree Synthesis2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)10.1109/ICERECT56837.2022.10059632(01-06)Online publication date: 26-Dec-2022
https://doi.org/10.1109/ICERECT56837.2022.10059632
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889756
Ewetz RTan CKoh CYoung EOzdal M(2016)Construction of Latency-Bounded Clock TreesProceedings of the 2016 on International Symposium on Physical Design10.1145/2872334.2872349(81-88)Online publication date: 3-Apr-2016
https://dl.acm.org/doi/10.1145/2872334.2872349
Han KLi JKahng ANath SLee J(2015)A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reductionProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744776(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744776
Yici Cai Chao Deng Qiang Zhou Hailong Yao Feifei Niu Sze C(2015)Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer InsertionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.230017423:1(142-155)Online publication date: Jan-2015
https://doi.org/10.1109/TVLSI.2014.2300174
Ewetz RKoh C(2015)Cost-Effective Robustness in Clock Networks Using Near-Tree StructuresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.239125334:4(515-528)Online publication date: Apr-2015
https://doi.org/10.1109/TCAD.2015.2391253
Deng CCai YZhou QChen Z(2015)An efficient buffer sizing algorithm for clock trees considering process variations2015 6th Asia Symposium on Quality Electronic Design (ASQED)10.1109/ACQED.2015.7274017(108-113)Online publication date: Aug-2015
https://doi.org/10.1109/ACQED.2015.7274017
Roy SMattheakis PMasse-Navette LPan D(2014)Evolving challenges and techniques for nanometer SoC clock network synthesis2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)10.1109/ICSICT.2014.7021158(1-4)Online publication date: Oct-2014
https://doi.org/10.1109/ICSICT.2014.7021158
YANG JCHANG I(2013)Robust Buffered Clock Tree Synthesis by Sensitivity Based Link InsertionIEICE Transactions on Electronics10.1587/transele.E96.C.127E96.C:1(127-131)Online publication date: 2013
https://doi.org/10.1587/transele.E96.C.127
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