Article

Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs

Authors:

Twan BastenAuthors Info & Claims

DAC '06: Proceedings of the 43rd annual Design Automation Conference

Pages 899 - 904

https://doi.org/10.1145/1146909.1147138

Published: 24 July 2006 Publication History

Abstract

Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute intensive kernels of these applications are often specified as Synchronous Dataflow Graphs. Communication between nodes in these graphs requires storage space which influences throughput. We present exact techniques to chart the Pareto space of throughput and storage trade-offs, which can be used to determine the minimal storage space needed to execute a graph under a given throughput constraint. The feasibility of the approach is demonstrated with a number of examples.

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Cited By

Letras MFalk JTeich J(2024)Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core SystemsIEEE Access10.1109/ACCESS.2024.337507912(39748-39769)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3375079
De Matteis TGianinazzi Lde Fine Licht JHoefler TButt AMi NChard K(2023)Streaming Task Graph Scheduling for Dataflow ArchitecturesProceedings of the 32nd International Symposium on High-Performance Parallel and Distributed Computing10.1145/3588195.3592999(225-237)Online publication date: 7-Aug-2023
https://dl.acm.org/doi/10.1145/3588195.3592999
Koh JBodin B(2022)K-Periodic Scheduling for Throughput-Buffering Trade-Off Exploration of CSDFACM Transactions on Embedded Computing Systems10.1145/355976022:1(1-28)Online publication date: 29-Oct-2022
https://dl.acm.org/doi/10.1145/3559760
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Index Terms

Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems

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cover image ACM Conferences

DAC '06: Proceedings of the 43rd annual Design Automation Conference

July 2006

1166 pages

ISBN:1595933816

DOI:10.1145/1146909

General Chair:
Ellen M. Sentovich
Cadence Berkeley Labs, Berkeley, CA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 24 July 2006

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July 24 - 28, 2006

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Letras MFalk JTeich J(2024)Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core SystemsIEEE Access10.1109/ACCESS.2024.337507912(39748-39769)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3375079
De Matteis TGianinazzi Lde Fine Licht JHoefler TButt AMi NChard K(2023)Streaming Task Graph Scheduling for Dataflow ArchitecturesProceedings of the 32nd International Symposium on High-Performance Parallel and Distributed Computing10.1145/3588195.3592999(225-237)Online publication date: 7-Aug-2023
https://dl.acm.org/doi/10.1145/3588195.3592999
Koh JBodin B(2022)K-Periodic Scheduling for Throughput-Buffering Trade-Off Exploration of CSDFACM Transactions on Embedded Computing Systems10.1145/355976022:1(1-28)Online publication date: 29-Oct-2022
https://dl.acm.org/doi/10.1145/3559760
Song SChong HBalaji ADas AShackleford JKandasamy N(2022)DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic HardwareACM Transactions on Embedded Computing Systems10.1145/347915621:3(1-35)Online publication date: 28-May-2022
https://dl.acm.org/doi/10.1145/3479156
Li ZWijerathne DChen XPathania AMitra T(2022)ChordMap: Automated Mapping of Streaming Applications Onto CGRAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305831341:2(306-319)Online publication date: Feb-2022
https://doi.org/10.1109/TCAD.2021.3058313
Das A(2022)Real-Time Scheduling of Machine Learning Operations on Heterogeneous Neuromorphic SoC2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)10.1109/MEMOCODE57689.2022.9954596(1-12)Online publication date: 13-Oct-2022
https://doi.org/10.1109/MEMOCODE57689.2022.9954596
Roumage GAzaiez SLouise S(2022)A survey of main dataflow MoCCs for CPS design and verification2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC57363.2022.00010(1-9)Online publication date: Dec-2022
https://doi.org/10.1109/MCSoC57363.2022.00010
Kouteili SSpagnuolo FBodin B(2022)Strictly Periodic Scheduling of Cyclo-Static Dataflow ModelsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_15(229-241)Online publication date: 27-Apr-2022
https://doi.org/10.1007/978-3-031-04580-6_15
Ma MSakellariou R(2021)Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore SystemsACM Transactions on Embedded Computing Systems10.1145/344003420:3(1-24)Online publication date: 27-Mar-2021
https://dl.acm.org/doi/10.1145/3440034
Song SVarshika MDas AKandasamy N(2021)A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643500(1-9)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643500
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