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Analysis and design of latch-controlled synchronous digital circuits

Authors:

Karem A. Sakallah,

Trevor N. Mudge,

Oyekunle A. OlukotunAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 111 - 117

https://doi.org/10.1145/123186.123237

Published: 03 January 1991 Publication History

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Abstract

We present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. We show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. We present an LP-based algorithm which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multi-phase overlapped clocks. We illustrate the formulation and an initial implementation of the algorithm on some example circuits.

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Cited By

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Chen NLi BSchlichtmann U(2011)Iterative timing analysis considering interdependency of setup and hold timesProceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation10.5555/2045364.2045372(73-82)Online publication date: 26-Sep-2011
https://dl.acm.org/doi/10.5555/2045364.2045372
Chen NLi BSchlichtmann U(2011)Timing modeling of flipflops considering aging effectsProceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation10.5555/2045364.2045371(63-72)Online publication date: 26-Sep-2011
https://dl.acm.org/doi/10.5555/2045364.2045371
Chen NLi BSchlichtmann U(2011)Iterative Timing Analysis Considering Interdependency of Setup and Hold TimesIntegrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation10.1007/978-3-642-24154-3_8(73-82)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24154-3_8
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Analysis and design of latch-controlled synchronous digital circuits

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Analysis and design of latch-controlled synchronous digital circuits

The authors present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. It is shown that the constraints are mildly nonlinear. The equivalence of the nonlinear optimal cycle time calculation problem to an ...
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is ...
Retiming Pulsed-Latch Circuits With Regulating Pulse Width

A pulsed-latch is an ideal sequencing element for high-performance application-specific integrated circuit designs due to its simple timing model and reduced sequencing overhead. The possibility of time-borrowing while a latch is transparent is ...

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Published In

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 03 January 1991

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DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

Florida, Orlando, USA

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DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Chen NLi BSchlichtmann U(2011)Iterative timing analysis considering interdependency of setup and hold timesProceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation10.5555/2045364.2045372(73-82)Online publication date: 26-Sep-2011
https://dl.acm.org/doi/10.5555/2045364.2045372
Chen NLi BSchlichtmann U(2011)Timing modeling of flipflops considering aging effectsProceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation10.5555/2045364.2045371(63-72)Online publication date: 26-Sep-2011
https://dl.acm.org/doi/10.5555/2045364.2045371
Chen NLi BSchlichtmann U(2011)Iterative Timing Analysis Considering Interdependency of Setup and Hold TimesIntegrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation10.1007/978-3-642-24154-3_8(73-82)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24154-3_8
Chen NLi BSchlichtmann U(2011)Timing Modeling of Flipflops Considering Aging EffectsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation10.1007/978-3-642-24154-3_7(63-72)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24154-3_7
Li BChen NSchlichtmann UScheffer LPhillips JHu A(2010)Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periodsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133540(524-531)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133540
Paik SYu LShin YLin Y(2010)Statistical time borrowing for pulsed-latch circuit designsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899879(675-680)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899879
Li BChen NSchlichtmann URoychowdhury J(2009)Timing model extraction for sequential circuits considering process variationsProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687463(336-343)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687463
Chen RZhou H(2004)Clock schedule verification under process variationsProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382650(619-625)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382650
Hassoun SCalvillo-Gámez ECromer C(2002)Verifying Clock Schedules in the Presence of Cross TalkProceedings of the conference on Design, automation and test in Europe10.5555/882452.874505Online publication date: 4-Mar-2002
https://dl.acm.org/doi/10.5555/882452.874505
Hassoun SDe Micheli G(2000)Critical path analysis using a dynamically bounded delay modelProceedings of the 37th Annual Design Automation Conference10.1145/337292.337413(260-265)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337413
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