Article

An effective hybrid transactional memory system with strong isolation guarantees

Authors:

Martin Trautmann,

JaeWoong Chung,

Austen McDonald,

Nathan Bronson,

Christos Kozyrakis,

Kunle OlukotunAuthors Info & Claims

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

Pages 69 - 80

https://doi.org/10.1145/1250662.1250673

Published: 09 June 2007 Publication History

Abstract

We propose signature-accelerated transactional memory (SigTM), ahybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the read-set and write-set forpending transactions and perform conflict detection between concurrent threads. All other transactional functionality, including dataversioning, is implemented in software. Unlike previously proposed hybrid TM systems, SigTM requires no modifications to the hardware caches, which reduces hardware cost and simplifies support for nested transactions and multithreaded processor cores. SigTM is also the first hybrid TM system to provide strong isolation guarantees between transactional blocks and non-transactional accesses without additional read and write barriers in non-transactional code.

Using a set of parallel programs that make frequent use of coarse-grain transactions, we show that SigTM accelerates software transactions by 30% to 280%. For certain workloads, SigTM can match the performance of a full-featured hardware TM system, while for workloads with large read-sets it can be up to two times slower. Overall, we show that SigTM combines the performance characteristics and strong isolation guarantees of hardware TM implementations with the low cost and flexibility of software TM systems.

References

[1]

A. Adl-Tabatabai, C. Kozyrakis, and B. Saha. Unlocking Concurrency: Multi-core programming with Transactional Memory. ACM Queue, 4(10), Dec. 2006.

Digital Library

[2]

A.-R. Adl-Tabatabai, B. Lewis, V. Menon, B.R. Murphy, B.Saha, and T.Shpeisman. Compiler and Runtime Support for Efficient Software Transactional Memory. In the Proceedings of the 2006 Conference on Programming Language Design and Implementation (PLDI), Ottawa, Canada, June 2006.

Digital Library

[3]

B. Bloom. Space/Time Trade-Offs in Hash Coding with Allowable Errors. Communications of ACM, 13(7), July 1970.

Digital Library

[4]

C. Blundell, E.C. Lewis, and M.M.K. Martin. Subtleties of Transactional Memory Atomicity Semantics. IEEE Computer Architecture Letters, 5(2), July 2006.

Digital Library

[5]

L. Ceze, J. Tuck, J. Torrellas, and C. Cascaval. Bulk Disambiguation of Speculative Threads in Multiprocessors. In the Proceedings of the 33rd Intl. Symposium on Computer Architecture (ISCA), June 2006.

Digital Library

[6]

H. Chafi, J. Casper, B.D. Carlstrom, A. McDonald, C. Cao-Minh, W. Baek, C. Kozyrakis, and K. Olukotun. A Scalable, Non-blocking Approach to Transactional Memory. In the Proceedings of the 13th Intl. Symposium on High Performance Computer Architecture (HPCA). Phoenix, AZ, Feb. 2007.

Digital Library

[7]

W. Chuang, S. Narayanasamy, G. Venkatesh, J. Sampson, M.V. Biesbrouck, G. Pokam, O. Colavin, and B. Calder. Unbounded Page-Based Transactional Memory. In the Proceedings of the 12th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). San Jose, CA, Oct. 2006.

Digital Library

[8]

J. Chung, C. Cao-Minh, A. McDonald, H. Chafi, B.D. Carlstrom, T. Skare, C. Kozyrakis, and K. Olukotun. Tradeoffs in Transactional Memory Virtualization.In the Proceedings of the 12th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). San Jose, CA, Oct. 2006.

Digital Library

[9]

J. Chung, H. Chafi, C. Cao-Minh, A. McDonald, B.D. Carlstrom, C. Kozyrakis, and K. Olukotun. The Common Case Transactional Behavior of Multithreaded Programs. In the Proceedings of the 12th Intl. Conference on High-Performance Computer Architecture (HPCA), Austin, TX, Feb. 2006.

[10]

P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In the Proceedings of the 12th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, Oct. 2006.

Digital Library

[11]

D. Dice, O. Shalev, and N. Shavit. Transactional Locking II. In the Proceedings of the 20th Intl. Symposium on Distributed Computing (DISC), Stockholm, Sweden, Sept. 2006.

Digital Library

[12]

D. Dice and N. Shavit. Understanding Tradeoffs in Software Transactional Memory. In the Proceedings of the Intl. Symposium on Code Generation and Optimization (CGO), San Jose, CA, Mar. 2007.

Digital Library

[13]

L. Hammond, V. Wong, M. Chen, B.D. Carlstrom, J.D. Davis, B. Hertzberg, M.K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional Memory Coherence and Consistency. In the Proceedings of the 31st Intl. Symposium on Computer Architecture (ISCA), Munich, Germany, June 2004.

Digital Library

[14]

T. Harris and K. Fraser. Language Support for Lightweight Transactions. In the Proceedings of the 18th Conference on Object-oriented Programing, Systems, Languages, and Applications (OOPSLA), Anaheim, CA, Oct. 2003.

Digital Library

[15]

T. Harris, M. Plesko, A. Shinnar, and D. Tarditi. Optimizing Memory Transactions. In the Proceedings of the Conference on Programming Language Design and Implementation (PLDI), Ottawa, Canada, June 2006.

Digital Library

[16]

M. Herlihy and J.E.B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In the Proceedings of the 20th Intl. Symposium on Computer Architecture (ISCA), San Diego, CA, May 1993.

Digital Library

[17]

S. Kumar, M. Chu, C.J. Hughes, P. Kundu, and A. Nguyen. Hybrid Transactional Memory. In the Proceedings of the 11th Symposium on Principles and Practice of Parallel Programming (PPoPP), New York, NY, Mar. 2006.

Digital Library

[18]

J. Larus and R. Rajwar. Transactional Memory. Morgan Claypool Synthesis Series, 2007.

[19]

V.J. Marathe, M.F. Spear, C. Heriot, A. Acharya, D. Eisenstat, W.N. Scherer, and M.L. Scott. Lowering the Overhead of Nonblocking Software Transactional Memory. In the Proceedings of the 1st Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, Ottawa, Canada, June 2006.

[20]

A. McDonald, J. Chung, B.D. Carlstrom, C. Cao-Minh, H. Chafi, C. Kozyrakis, and K. Olukotun. Architectural Semantics for Practical Transactional Memory. In the Proceedings of the 33rd Intl. Symposium on Computer Architecture (ISCA), Bostom, MA, June 2006.

Digital Library

[21]

K.E. Moore, J. Bobba, M.J. Moravan, M.D. Hill, and D.A. Wood. LogTM: Log-Based Transactional Memory. In the Proceedings of the 12th Intl. Conference on High-Performance Computer Architecture (HPCA), Austin, TX, Feb. 2006.

[22]

R. Rajwar, M. Herlihy, and K. Lai. Virtualizing Transactional Memory. In the Proceedings of the 32nd Intel. Symposium on Computer Architecture (ISCA), Madison, WI, June 2005.

Digital Library

[23]

B. Saha, A.-R. Adl-Tabatabai, R.L. Hudson, C. Cao-Minh, and B. Hertzberg. A High Performance Software Transactional Memory System For A Multi-Core Runtime. In the Proceedings of the 11th Symposium on Principles and practice of Parallel Programming (PPoPP), New York, NY, Mar. 2006.

Digital Library

[24]

B. Saha, A.-R. Adl-Tabatabai, and Q. Jacobson. Architectural Support for Software Transactional Memory. In the Proceedings of the 39th Intl. Symposium on Microarchitecture (MICRO), Orlando, FL, Dec. 2006.

Digital Library

[25]

T. Shpeisman, V. Menon, A.-R. Adl-Tabatabai1, S. Balensiefer, D. Grossman, R.L. Hudson, K. Moore, and B. Saha. Enforcing Isolation and Ordering in STM. In the Proceedings of the 2007 Conference on Programming Language Design and Implementation (PLDI), Mar. 2007.

Digital Library

[26]

S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta. The SPLASH2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24--36, June 1995.

Digital Library

[27]

L. Yen, J. Bobba, M.R. Marty, K.E. Moore, H. Volos, M.D. Hill, M.M. Swift, and D.A. Wood. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. In the Proceedings of the 13th Intl. Symposium on High Performance Computer Architecture (HPCA), Feb. 2007.

Digital Library

Cited By

Zeng JJeong JJung C(2023)Persistent Processor ArchitectureProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623772(1075-1091)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3623772
Kim SHan MBaek W(2022)DPrime+DAbort: A High-Precision and Timer-Free Directory-Based Side-Channel Attack in Non-Inclusive Cache Hierarchies using Intel TSX2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00014(67-81)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00014
Li ZLiu LDeng YWang JLiu ZYin SWei S(2019)FPGA-Accelerated Optimistic Concurrency Control for Transactional MemoryProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358270(911-923)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358270
Show More Cited By

Index Terms

An effective hybrid transactional memory system with strong isolation guarantees

Recommendations

Hybrid transactional memory
ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems

Transactional memory (TM) promises to substantially reduce the difficulty of writing correct, efficient, and scalable concurrent programs. But "bounded" and "best-effort" hardware TM proposals impose unreasonable constraints on programmers, while more ...
An effective hybrid transactional memory system with strong isolation guarantees

We propose signature-accelerated transactional memory (SigTM), ahybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the read-set and write-set forpending transactions and perform conflict ...
Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS Conference

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

June 2007

542 pages

ISBN:9781595937063

DOI:10.1145/1250662

General Chair:
Dean Tullsen
University of California, San Diego
,
Program Chair:
Brad Calder
Microsoft & University of California, San Diego

ACM SIGARCH Computer Architecture News Volume 35, Issue 2
May 2007
527 pages
ISSN:0163-5964
DOI:10.1145/1273440
Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 June 2007

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

SPAA07

Sponsor:

SIGARCH
IEEE-CS

SPAA07: 19th ACM Symposium on Parallelism in Algorithms and Architectures

June 9 - 13, 2007

California, San Diego, USA

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

225
Total Citations
View Citations
1,275
Total Downloads

Downloads (Last 12 months)24
Downloads (Last 6 weeks)3

Reflects downloads up to 13 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Zeng JJeong JJung C(2023)Persistent Processor ArchitectureProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623772(1075-1091)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3623772
Kim SHan MBaek W(2022)DPrime+DAbort: A High-Precision and Timer-Free Directory-Based Side-Channel Attack in Non-Inclusive Cache Hierarchies using Intel TSX2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00014(67-81)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00014
Li ZLiu LDeng YWang JLiu ZYin SWei S(2019)FPGA-Accelerated Optimistic Concurrency Control for Transactional MemoryProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358270(911-923)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358270
Saad MPalmieri RRavindran B(2019)LernaACM Transactions on Storage10.1145/331036815:1(1-24)Online publication date: 22-Mar-2019
https://dl.acm.org/doi/10.1145/3310368
Shang ZYu JZhang Z(2019)TuFast: A Lightweight Parallelization Library for Graph Analytics2019 IEEE 35th International Conference on Data Engineering (ICDE)10.1109/ICDE.2019.00069(710-721)Online publication date: Apr-2019
https://doi.org/10.1109/ICDE.2019.00069
Park JBaek W(2019)Analyzing and optimizing the performance and energy efficiency of transactional scientific applications on large-scale NUMA systems with HTM supportJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.12.007127:C(1-17)Online publication date: 1-May-2019
https://dl.acm.org/doi/10.1016/j.jpdc.2018.12.007
Saad MPalmieri RRavindran BBreitgand DYadgar GPorter DEyal I(2018)LernaProceedings of the 11th ACM International Systems and Storage Conference10.1145/3211890.3211897(37-48)Online publication date: 4-Jun-2018
https://dl.acm.org/doi/10.1145/3211890.3211897
Zhang DFu HHan JBorji ALi X(2018)A Review of Co-Saliency Detection AlgorithmsACM Transactions on Intelligent Systems and Technology10.1145/31586749:4(1-31)Online publication date: 30-Jan-2018
https://dl.acm.org/doi/10.1145/3158674
Park JBaek W(2018)Quantifying the Performance and Energy-Efficiency Impact of Hardware Transactional Memory on Scientific Applications on Large-Scale NUMA Systems2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS.2018.00090(804-813)Online publication date: May-2018
https://doi.org/10.1109/IPDPS.2018.00090
Ren XLis M(2018)High-Performance GPU Transactional Memory via Eager Conflict Detection2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00029(235-246)Online publication date: Feb-2018
https://doi.org/10.1109/HPCA.2018.00029
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents