Article

Matrix scheduler reloaded

Authors:

Peter G. Sassone,

Jeff Rupley, II,

Edward Brekelbaum,

Gabriel H. Loh,

Bryan BlackAuthors Info & Claims

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

Pages 335 - 346

https://doi.org/10.1145/1250662.1250704

Published: 09 June 2007 Publication History

Abstract

From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within power and latency bounds. This tension is quite evident in schedulers, which need to be large and single-cycle for maximum performance on out-of-order cores. In this work we present two straightforward modifications to a matrix scheduler implementation which greatly strengthen its scalability. Both are based on the simple observation that the wakeup and picker matrices are sparse, even at small sizes; thus small indirection tables can be used to greatly reduce their width and latency. This technique can be used to create quicker iso-performance schedulers (17-58% reduced critical path) or larger iso-timing schedulers (7-26% IPC increase). Importantly, the power and area requirements of the additional hardware are likely offset by the greatly reduced matrix sizes and subsuming the functionality of the power-hungry allocation CAMs.

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Cited By

Huerta RArnau JGonzalez A(2023)Simple Out of Order Core for GPGPUsProceedings of the 15th Workshop on General Purpose Processing Using GPU10.1145/3589236.3589244(21-26)Online publication date: 25-Feb-2023
https://dl.acm.org/doi/10.1145/3589236.3589244
Gast SJuffinger JSchwarzl MSaileshwar GKogler AFranza SKöstl MGruss D(2023)SQUIP: Exploiting the Scheduler Queue Contention Side Channel2023 IEEE Symposium on Security and Privacy (SP)10.1109/SP46215.2023.10179368(2256-2272)Online publication date: May-2023
https://doi.org/10.1109/SP46215.2023.10179368
Michaud PPeysieux A(2022)HAIR: Halving the Area of the Integer Register File with Odd/Even BankingACM Transactions on Architecture and Code Optimization10.1145/354483819:4(1-25)Online publication date: 16-Sep-2022
https://dl.acm.org/doi/10.1145/3544838
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Index Terms

Matrix scheduler reloaded
1. Computer systems organization
  1. Architectures

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Published In

cover image ACM Conferences

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

June 2007

542 pages

ISBN:9781595937063

DOI:10.1145/1250662

General Chair:
Dean Tullsen
University of California, San Diego
,
Program Chair:
Brad Calder
Microsoft & University of California, San Diego

ACM SIGARCH Computer Architecture News Volume 35, Issue 2
May 2007
527 pages
ISSN:0163-5964
DOI:10.1145/1273440
Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 09 June 2007

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SPAA07: 19th ACM Symposium on Parallelism in Algorithms and Architectures

June 9 - 13, 2007

California, San Diego, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Huerta RArnau JGonzalez A(2023)Simple Out of Order Core for GPGPUsProceedings of the 15th Workshop on General Purpose Processing Using GPU10.1145/3589236.3589244(21-26)Online publication date: 25-Feb-2023
https://dl.acm.org/doi/10.1145/3589236.3589244
Gast SJuffinger JSchwarzl MSaileshwar GKogler AFranza SKöstl MGruss D(2023)SQUIP: Exploiting the Scheduler Queue Contention Side Channel2023 IEEE Symposium on Security and Privacy (SP)10.1109/SP46215.2023.10179368(2256-2272)Online publication date: May-2023
https://doi.org/10.1109/SP46215.2023.10179368
Michaud PPeysieux A(2022)HAIR: Halving the Area of the Integer Register File with Odd/Even BankingACM Transactions on Architecture and Code Optimization10.1145/354483819:4(1-25)Online publication date: 16-Sep-2022
https://dl.acm.org/doi/10.1145/3544838
Ando H(2022)Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00059(360-363)Online publication date: Oct-2022
https://doi.org/10.1109/ICCD56317.2022.00059
Spasov D(2020)A Circuit for Identifying Oldest Ready Instructions in Reservation Stations2020 43rd International Convention on Information, Communication and Electronic Technology (MIPRO)10.23919/MIPRO48935.2020.9245125(109-113)Online publication date: 28-Sep-2020
https://doi.org/10.23919/MIPRO48935.2020.9245125
Mashimo SInoue KShioya RFujita AMatsuo RAkaki SFukuda AKoizumi TKadomoto JIrie HGoshima M(2019)An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00016(63-71)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00016
Wong HBetz VRose J(2018)High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft ProcessorsACM Transactions on Reconfigurable Technology and Systems10.1145/309374111:1(1-22)Online publication date: 9-Jan-2018
https://dl.acm.org/doi/10.1145/3093741
Ando HOskin MInoue K(2018)Performance improvement by prioritizing the issue of the instructions in unconfident branch slicesProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00016(82-94)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00016
Sakai SSuenaga TShioya RAndo H(2018)Rearranging Random Issue Queue with High IPC and Short Delay2018 IEEE 36th International Conference on Computer Design (ICCD)10.1109/ICCD.2018.00027(123-131)Online publication date: Oct-2018
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Perais AEndo FSeznec AHsu WYang CLipasti MLee H(2016)Register sharing for equality predictionThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195643(1-12)Online publication date: 15-Oct-2016
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