article

Making the fast case common and the uncommon case simple in unbounded transactional memory

Authors:

Colin Blundell,

E. Christopher Lewis,

Milo M. K. MartinAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 2

Pages 24 - 34

https://doi.org/10.1145/1273440.1250667

Published: 09 June 2007 Publication History

Abstract

Hardware transactional memory has great potential to simplify the creation ofcorrect and efficient multithreaded programs, allowing programmers to exploitmore effectively the soon-to-be-ubiquitous multi-core designs. Several recentproposals have extended the original bounded transactional memory to unboundedtransactional memory, a crucial step toward transactions becoming ageneral-purpose primitive. Unfortunately, supporting the concurrent executionof an unbounded number of unbounded transactions is challenging, and as aresult, many proposed implementations are complex.

This paper explores a different approach. First, we introduce thepermissions-only cache to extend the bound at which transactions overflow toallow the fast, bounded case to be used as frequently as possible. Second, wepropose OneTM to simplify the implementation of unbounded transactional memoryby bounding the concurrency of transactions that overflow the cache. Thesemechanisms work synergistically to provide a simple and fast unboundedtransactional memory system.

The permissions-only cache efficiently maintains the coherencepermissions-but not data-for blocks read or written transactionally thathave been evicted from the processor's caches. By holding coherencepermissions for these blocks, the regular cache coherence protocol can be usedto detect transactional conflicts using only a few bits of on-chip storage peroverflowed cache block.OneTM allows only one overflowed transaction at a time, relying on thepermissions-only cache to ensure that overflow is infrequent. We present twoimplementations. In OneTM-Serialized, an overflowed transaction simply stallsall other threads in the application.

In OneTM-Concurrent, non-overflowedtransactions and non-transactional code can execute concurrently with theoverflowed transaction, providing more concurrency while retaining OneTM's coresimplifying assumption.

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Cited By

Piatka CAmslinger RHaas FWeis SAltmeyer SUngerer T(2020)Investigating Transactional Memory for High Performance Embedded SystemsArchitecture of Computing Systems – ARCS 202010.1007/978-3-030-52794-5_8(97-108)Online publication date: 25-May-2020
https://dl.acm.org/doi/10.1007/978-3-030-52794-5_8
Ruppel ELucia BMcKinley KFisher K(2019)Transactional concurrency control for intermittent, energy-harvesting computing systemsProceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3314221.3314583(1085-1100)Online publication date: 8-Jun-2019
https://dl.acm.org/doi/10.1145/3314221.3314583
Liu YXia YGuan HZang BChen H(2014)Concurrent and consistent virtual machine introspection with hardware transactional memory2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2014.6835951(416-427)Online publication date: Feb-2014
https://doi.org/10.1109/HPCA.2014.6835951
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Index Terms

Making the fast case common and the uncommon case simple in unbounded transactional memory
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 2

May 2007

527 pages

ISSN:0163-5964

DOI:10.1145/1273440

Issue’s Table of Contents

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture
June 2007
542 pages
ISBN:9781595937063
DOI:10.1145/1250662
General Chair:
Dean Tullsen
University of California, San Diego
,
Program Chair:
Brad Calder
Microsoft & University of California, San Diego

Copyright © 2007 ACM.

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Published: 09 June 2007

Published in SIGARCH Volume 35, Issue 2

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Cited By

Piatka CAmslinger RHaas FWeis SAltmeyer SUngerer T(2020)Investigating Transactional Memory for High Performance Embedded SystemsArchitecture of Computing Systems – ARCS 202010.1007/978-3-030-52794-5_8(97-108)Online publication date: 25-May-2020
https://dl.acm.org/doi/10.1007/978-3-030-52794-5_8
Ruppel ELucia BMcKinley KFisher K(2019)Transactional concurrency control for intermittent, energy-harvesting computing systemsProceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3314221.3314583(1085-1100)Online publication date: 8-Jun-2019
https://dl.acm.org/doi/10.1145/3314221.3314583
Liu YXia YGuan HZang BChen H(2014)Concurrent and consistent virtual machine introspection with hardware transactional memory2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2014.6835951(416-427)Online publication date: Feb-2014
https://doi.org/10.1109/HPCA.2014.6835951
Scott M(2013)Shared-Memory SynchronizationSynthesis Lectures on Computer Architecture10.2200/S00499ED1V01Y201304CAC0238:2(1-221)Online publication date: 12-Jun-2013
https://doi.org/10.2200/S00499ED1V01Y201304CAC023
Korgaonkar KJain PTomar DGarimella KKamakoti V(2011)Reconstructing hardware transactional memory for workload optimized systemsProceedings of the 9th international conference on Advanced parallel processing technologies10.5555/2042522.2042523(1-15)Online publication date: 26-Sep-2011
https://dl.acm.org/doi/10.5555/2042522.2042523
Dalessandro LCarouge FWhite SLev YMoir MScott MSpear M(2011)Hybrid NOrecACM SIGPLAN Notices10.1145/1961296.195037346:3(39-52)Online publication date: 5-Mar-2011
https://dl.acm.org/doi/10.1145/1961296.1950373
Dalessandro LCarouge FWhite SLev YMoir MScott MSpear M(2011)Hybrid NOrecACM SIGARCH Computer Architecture News10.1145/1961295.195037339:1(39-52)Online publication date: 5-Mar-2011
https://dl.acm.org/doi/10.1145/1961295.1950373
Dalessandro LCarouge FWhite SLev YMoir MScott MSpear MGupta RMowry T(2011)Hybrid NOrecProceedings of the sixteenth international conference on Architectural support for programming languages and operating systems10.1145/1950365.1950373(39-52)Online publication date: 5-Mar-2011
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Korgaonkar KJain PTomar DGarimella KKamakoti V(2011)Reconstructing Hardware Transactional Memory for Workload Optimized SystemsAdvanced Parallel Processing Technologies10.1007/978-3-642-24151-2_1(1-15)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24151-2_1
Wang XJi ZFu CHu M(2010)A Review of Transactional Memory in Multicore ProcessorsInformation Technology Journal10.3923/itj.2010.192.2009:1(192-200)Online publication date: 1-Jan-2010
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