research-article

FPGA area reduction by multi-output function based sequential resynthesis

Authors:

Rupak Majumdar, and

Lei HeAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

Pages 24 - 29

https://doi.org/10.1145/1391469.1391478

Published: 08 June 2008 Publication History

Abstract

We propose a new resynthesis algorithm for FPGA area reduction. In contrast to existing resynthesis techniques, which consider only single-output Boolean functions and the combinational portion of a circuit, we consider multi-output functions and retiming, and develop effective algorithms that incorporate recent improvements to SAT-based Boolean matching. Our experimental results show that with the optimal logic depth, the resynthesis considering multi-output functions reduces area by up to 0.4% compared to the one considering single-output functions, and the sequential resynthesis reduces area by up to 10% compared to combinational resynthesis when both consider multi-output functions. Furthermore, our proposed resynthesis algorithm reduces area by up to 16% compared to the best existing academic technology mapper, Berkeley ABC.

References

[1]

A. Farrahi and M. Sarrafzadeh, "Complexity of the lookup-table minimization problem for fpga technology mapping," TCAD, 1994.

[2]

J. Cong and Y. Ding, "On area/depth trade-off in lut-based FPGA technology mapping," DAC, 1993.

Digital Library

[3]

J. Cong and Y.-Y. Hwang, "Simultaneous depth and area minimization in lut-based fgpa mapping," FPGA, 1995.

Digital Library

[4]

V. Manohararajah, S. D. Brown, and Z. G. Vranesic, "Heuristics for area minimization in lut-based fpga technology mapping," IWLS, 2004.

[5]

D. Chen and J. Cong, "Daomap: A depth-optimal area optimization mapping algorithm for fpga designs," ICCAD, 2004.

Digital Library

[6]

"Abc: A system for sequential synthesis and verification," in http://www.eecs.berkeley.edu/alumni/abc/.

[7]

A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to technology mapping for lut-based fpgas," FPGA, 2006.

Digital Library

[8]

K. Minkovich and J. Cong, "Optimality study of logic synthesis for lut-based fpgas," FPGA, 2006.

Digital Library

[9]

G. D. Micheli, "Synchronous logic synthesis: algorithms for cycle-time minimization," TCAD, 1991.

[10]

A. Mishchenko, S. Chatterjee, and R. Brayton, "Dag-aware aig rewriting," DAC, 2005.

[11]

S. Malik, E. Sentovich, R. Brayton, and A. Sangiovanni-Vincentelli, "Retiming and resynthesis: Optimizing sequential networks with combinational techniques," TCAD, 1991.

[12]

R. Brayton and A. Mishchenko, "Sequential rewriting," IWLS, 2007.

[13]

E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, "Logic decomposition during technology mapping," TCAD, 1997.

Digital Library

[14]

A. Mishchenko, X. Wang, and T. Kam, "A new enhanced constructive decomposition and mapping algorithm," DAC, 2003.

Digital Library

[15]

A. Ling, D. Singh, and S. Brown, "FPGA technology mapping: a study of optimality," DAC, 2005.

Digital Library

[16]

J. Cong and K. Minkovich, "Improved sat-based boolean matching using implicants for lut-based fpgas," FPGA, 2007.

Digital Library

[17]

L. Benini and G. D. Micheli, "A survey of Boolean matching techniques for library binding," TODAES, 1997.

Digital Library

[18]

Y. Hu, V. Shih, R. Majumdar, and L. He, "Exploiting symmetry in satbased boolean matching for heterogeneous fpga technology mapping," ICCAD, 2007.

Digital Library

[19]

S. Safarpour, A. Veneris, G. Baeckler, and R. Yuan, "Efficient sat based boolean matching for fpga technology mapping," DAC, 2006.

Digital Library

[20]

Y. Hu, S. Das, S. Trimberger, and L. He, "Design, synthesis and evaluation of heterogeneous fpga with mixed luts and macro-gates," ICCAD, 2007.

Digital Library

[21]

A. Mishchenko and R. Brayton, "Sat-based complete dontcare computation for network optimization," DATe, 2005.

Digital Library

[22]

J. Cong, C. Wu, and Y. Ding, "Cut ranking and pruning: Enabling a general and efficient fpga mapping solution," FPGA, 1999.

Digital Library

[23]

C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, 1991.

[24]

Z. Xiu, D. A. Papa, P. Chong, A. Kuehlmann, R. A. Rutenbar, and I. L. Markov, "Early research experience with openaccess gear:," ISPD, 2005.

Digital Library

[25]

N. Een and N. Sorensso, http://www.cs.chalmers.se/Cs/Research/ FormalMethods/MiniSat/MiniSat.html.

[26]

MCNC, MCNC Designers' Manual, 1993.

[27]

"Iwls 2005 benchmarks," in http://iwls.org/iwls2005/benchmarks.html.

[28]

P. Pan and C.-C. Lin, "A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs," FPGA, 1998

Digital Library

Cited By

Liu GZhang Z(2019)PIMapACM Transactions on Reconfigurable Technology and Systems10.1145/326834411:4(1-23)Online publication date: 9-Jan-2019
https://dl.acm.org/doi/10.1145/3268344
Liu GZhang ZGreene JAnderson J(2017)A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology MappingProceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3020078.3021735(147-156)Online publication date: 22-Feb-2017
https://dl.acm.org/doi/10.1145/3020078.3021735
Sanchez-Macian AReviriego PMaestro J(2016)Optimizing the Implementation of SEC–DAEC Codes in FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.255694324:12(3538-3542)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2556943
Show More Cited By

Index Terms

FPGA area reduction by multi-output function based sequential resynthesis
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and Resynthesis
EDTC '97: Proceedings of the 1997 European conference on Design and Test

This paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, e.g., the monotonous cover ...
Read More
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits
VTS '95: Proceedings of the 13th IEEE VLSI Test Symposium

Abstract: In pseudo-exhaustive testing, the partitioning technique consists of placing segmentation cells in an acyclic sequential circuit in order to reduce the size of cones. These segmentations, which are transparent in normal mode and active during ...
Read More
FPGA glitch power analysis and reduction
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

This paper presents a don't-care-based synthesis technique for reducing glitch power in FPGAs. First, an analysis of glitch power and don't-cares in a commercial FPGA is given, showing that glitch power comprises an average of 26.0% of total dynamic ...
Read More

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

The EDA Consortium
IEEE/CASS/CANDE/CEDA
SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 June 2008

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Conference

DAC '08

Sponsor:

SIGDA

DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
209
Total Downloads

Downloads (Last 12 months)8
Downloads (Last 6 weeks)1

Other Metrics

View Author Metrics

Citations

Cited By

Liu GZhang Z(2019)PIMapACM Transactions on Reconfigurable Technology and Systems10.1145/326834411:4(1-23)Online publication date: 9-Jan-2019
https://dl.acm.org/doi/10.1145/3268344
Liu GZhang ZGreene JAnderson J(2017)A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology MappingProceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3020078.3021735(147-156)Online publication date: 22-Feb-2017
https://dl.acm.org/doi/10.1145/3020078.3021735
Sanchez-Macian AReviriego PMaestro J(2016)Optimizing the Implementation of SEC–DAEC Codes in FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.255694324:12(3538-3542)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2556943
Das NRoy PRahaman H(2014)Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)Journal of The Institution of Engineers (India): Series B10.1007/s40031-014-0141-996:3(227-236)Online publication date: 15-Jul-2014
https://doi.org/10.1007/s40031-014-0141-9
Hu YFeng ZHe LMajumdar RNassif SRoychowdhury J(2008)Robust FPGA resynthesis based on fault-tolerant Boolean matchingProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509611(706-713)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509611

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents