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A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers

Authors:

Mingche Lai,

Zhiying Wang,

Lei Gao,

Hongyi Lu,

Kui DaiAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 630 - 633

https://doi.org/10.1145/1391469.1391630

Published: 08 June 2008 Publication History

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Abstract

In this paper, the dynamically-allocated virtual channels (VCs) architecture with congestion awareness is introduced. All the buffers are shared among VCs whose structure varies with traffic condition. In low rate, this structure extends VC depth for continual transfers to reduce packet latencies. In high rate, it dispenses many VCs and avoids congestion situations to improve the throughput. We modify the VC controller and VC allocation modules, while designing simple congestion avoidance logic. The experiment shows that the proposed routers outperform conventional ones under different traffic patterns. They provide 8.3% throughput increase and 19.6% latency decrease while saving 27.4% of area and 28.6% of power.

References

[1]

X. Chen, et. al. Leakage Power Modeling and Optimization in Interconnection Networks. In Proc. of the ISLPED conference, 2002.

Digital Library

Google Scholar

[2]

Ting-Chun Huang, et. al. Virtual Channels Planning for Networks-on-Chip. In Proc. of the ISQED conference, 2007.

Digital Library

Google Scholar

[3]

Y. Tamir, et. al. High-performance multiqueue buffers for VLSI communication Switches. In Proc. of the ISCA conference, 1988.

Digital Library

Google Scholar

[4]

C. A. Nicopoulos, et. al. ViChaR: A Dynamic Virtual Channel Regulator for Network-on-chip Router. In Proc. of the Micro conference, 2006.

Digital Library

Google Scholar

[5]

Li-Shiuan Peh, et. al. A Delay Model and Speculative Architecture for Pipelined Router. In Proc. of the HPCA conference, 2001.

Digital Library

Google Scholar

[6]

M. Rezazad, et. al. The effect of virtual channel organization on the performance of interconnection networks. In Proc. of the IPDPS, 2005.

Digital Library

Google Scholar

[7]

Yihan Li, et. al. Performance analysis of a dual round robin matching switch with exhaustive service. In Proc. of the GLOBECOM, 2002.

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Yadav SLaxmi VKapoor HGaur MKumar A(2023)Adaptive distribution of control messages for improving bandwidth utilization in multiple NoCThe Journal of Supercomputing10.1007/s11227-023-05208-079:15(17208-17246)Online publication date: 7-May-2023
https://doi.org/10.1007/s11227-023-05208-0
Tsai WLin HLan YChen S(2022)Anticipative QoS Control: A Self-Reconfigurable On-Chip CommunicationMicromachines10.3390/mi1310166913:10(1669)Online publication date: 4-Oct-2022
https://doi.org/10.3390/mi13101669
Gong SLi JLu WYan GLi X(2021)ShuntFlowPlus: An Efficient and Scalable Dataflow Accelerator Architecture for Stream ApplicationsACM Journal on Emerging Technologies in Computing Systems10.1145/345316417:4(1-24)Online publication date: 30-Jun-2021
https://dl.acm.org/doi/10.1145/3453164
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Index Terms

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers
1. Hardware
  1. Integrated circuits
    1. Interconnect

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Published In

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 08 June 2008

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Yadav SLaxmi VKapoor HGaur MKumar A(2023)Adaptive distribution of control messages for improving bandwidth utilization in multiple NoCThe Journal of Supercomputing10.1007/s11227-023-05208-079:15(17208-17246)Online publication date: 7-May-2023
https://doi.org/10.1007/s11227-023-05208-0
Tsai WLin HLan YChen S(2022)Anticipative QoS Control: A Self-Reconfigurable On-Chip CommunicationMicromachines10.3390/mi1310166913:10(1669)Online publication date: 4-Oct-2022
https://doi.org/10.3390/mi13101669
Gong SLi JLu WYan GLi X(2021)ShuntFlowPlus: An Efficient and Scalable Dataflow Accelerator Architecture for Stream ApplicationsACM Journal on Emerging Technologies in Computing Systems10.1145/345316417:4(1-24)Online publication date: 30-Jun-2021
https://dl.acm.org/doi/10.1145/3453164
Gangwar ASreedharan RPrasad AAgarwal NGade S(2021)Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586196(61-66)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586196
Gangwar AAgarwal NSreedharan RPrasad AGade SXu ZXie Y(2020)Automated synthesis of custom networks-on-chip for real world applicationsProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415656(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415656
P SKanumuri NAK SVenkata Sateesh V(2020)Intellectual Completion Tracking System Micro-architecture for Advanced NoC Designs2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)10.1109/VLSIDCS47293.2020.9179889(70-73)Online publication date: Jul-2020
https://doi.org/10.1109/VLSIDCS47293.2020.9179889
Lan YMuthukumar V(2017)Efficient virtual channel allocator for NoC router micro-architecture2017 30th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2017.8226030(169-174)Online publication date: Sep-2017
https://doi.org/10.1109/SOCC.2017.8226030
Monemi ATang JPalesi MMarsono M(2017)ProNoCMicroprocessors & Microsystems10.1016/j.micpro.2017.08.00754:C(60-74)Online publication date: 1-Oct-2017
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Oveis-Gharan MKhan G(2016)Efficient Dynamic Virtual Channel Organization and Architecture for NoC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.240593324:2(465-478)Online publication date: Feb-2016
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Hassan HSaid MKim H(2016)Performance evaluation of buffer sharing routers for Network on Chip2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2016.7869977(1-4)Online publication date: Oct-2016
https://doi.org/10.1109/MWSCAS.2016.7869977
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Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers

Virtual channels in networks on chip: implementation and evaluation on hermes NoC

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Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers

Virtual channels in networks on chip: implementation and evaluation on hermes NoC

Enhanced global congestion awareness (EGCA) for load balance in networks-on-chip

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