research-article

Understanding the interconnection network of SpiNNaker

Authors:

Javier Navaridas,

Jose Miguel-Alonso,

Steve FurberAuthors Info & Claims

ICS '09: Proceedings of the 23rd international conference on Supercomputing

Pages 286 - 295

https://doi.org/10.1145/1542275.1542317

Published: 08 June 2009 Publication History

Abstract

SpiNNaker is a massively parallel architecture designed to model large-scale spiking neural networks in (biological) real-time. Its design is based around ad-hoc multi-core System-on-Chips which are interconnected using a two-dimensional toroidal triangular mesh. Neurons are modeled in software and their spikes generate packets that propagate through the on- and inter-chip communication fabric relying on custom-made on-chip multicast routers. This paper models and evaluates large-scale instances of its novel interconnect (more than 65 thousand nodes, or over one million computing cores), focusing on real-time features and fault-tolerance. The key contribution can be summarized as understanding the properties of the feasible topologies and establishing the stable operation of the SpiNNaker under different levels of degradation. First we derive analytically the topological characteristics of the network, which are later confirmed by experimental work. With the computational model developed, we investigate the topology of SpiNNaker, and compare it with a standard 3-dimensional torus. The novel emergency routing mechanism, implemented within the routers, allows the topology of SpiNNaker to be more robust than the 3-dimensional torus, regardless of the latter having better topological characteristics. Furthermore, we obtain optimal values of two router parameters related with livelock and deadlock avoidance mechanisms.

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https://doi.org/10.1109/TETCI.2024.3379165
Frenkel CBol DIndiveri G(2023)Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial IntelligenceProceedings of the IEEE10.1109/JPROC.2023.3273520111:6(623-652)Online publication date: Jun-2023
https://doi.org/10.1109/JPROC.2023.3273520
Xiao CLou HLi CJin K(2020)DBM: A Dimension-Bubble-Based Multicast Routing Algorithm for 2D Mesh Network-on-ChipsAdvanced Computer Architecture10.1007/978-981-15-8135-9_4(43-55)Online publication date: 5-Sep-2020
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Understanding the interconnection network of SpiNNaker

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Published In

cover image ACM Conferences

ICS '09: Proceedings of the 23rd international conference on Supercomputing

June 2009

544 pages

ISBN:9781605584980

DOI:10.1145/1542275

General Chairs:
Michael Gschwind
IBM TJ Watson Research Center, USA
,
Alex Nicolau
UC Irvine, USA
,
Program Chairs:
Valentina Salapura
IBM TJ Watson Research Center, USA
,
José Moreira
IBM TJ Watson Research Center, USA

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 June 2009

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June 8 - 12, 2009

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

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https://doi.org/10.1109/TETCI.2024.3379165
Frenkel CBol DIndiveri G(2023)Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial IntelligenceProceedings of the IEEE10.1109/JPROC.2023.3273520111:6(623-652)Online publication date: Jun-2023
https://doi.org/10.1109/JPROC.2023.3273520
Xiao CLou HLi CJin K(2020)DBM: A Dimension-Bubble-Based Multicast Routing Algorithm for 2D Mesh Network-on-ChipsAdvanced Computer Architecture10.1007/978-981-15-8135-9_4(43-55)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_4
Frenkel CLegat JBol D(2019)MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online LearningIEEE Transactions on Biomedical Circuits and Systems10.1109/TBCAS.2019.292879313:5(999-1010)Online publication date: Oct-2019
https://doi.org/10.1109/TBCAS.2019.2928793
Frenkel CLegat JBol D(2019) A 65-nm 738k-Synapse/mm 2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning 2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702793(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702793
Andreou AMendat D(2019)Graphical Model Transformation Analysis for Cognitive Computing and Machine Learning on the SpiNNaker Chip Multiprocessor2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00112(299-304)Online publication date: Aug-2019
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Bogdan PRowley ARhodes OFurber S(2018)Structural Plasticity on the SpiNNaker Many-Core Neuromorphic SystemFrontiers in Neuroscience10.3389/fnins.2018.0043412Online publication date: 2-Jul-2018
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Pastur-Romay LCedrón FPazos APorto-Pazos A(2016)Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics ApplicationsInternational Journal of Molecular Sciences10.3390/ijms1708131317:8(1313)Online publication date: 11-Aug-2016
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Katevenis MChrysos NMarazakis MMavroidis IChaix FKallimanis NNavaridas JGoodacre JVicini PBiagioni APaolucci PLonardo APastorelli ECicero FAmmendola RHopton PCoates PTaffoni GCozzini SKersten MZhang YSahuquillo JLechago SPinto CLietzow BEverett DPerna G(2016)The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems2016 Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2016.106(60-67)Online publication date: Aug-2016
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