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An efficient method of partitioning circuits for multiple-FPGA implementation.

Authors:

Nam Sung Woo,

Jaeseok KimAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 202 - 207

https://doi.org/10.1145/157485.164669

Published: 01 July 1993 Publication History

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Tomesh TSaleem ZPerlin MGokhale PSuchara MMartonosi M(2023)Divide and Conquer for Combinatorial Optimization and Distributed Quantum Computation2023 IEEE International Conference on Quantum Computing and Engineering (QCE)10.1109/QCE57702.2023.00009(1-12)Online publication date: 17-Sep-2023
https://doi.org/10.1109/QCE57702.2023.00009
Mao FZhang WFeng BHe BMa YCoskun AMargala MBehjat LHan J(2016)Modular Placement for Interposer based Multi-FPGA SystemsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903025(93-98)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903025
Fleming KAdler MPellauer MParashar AMithal AEmer JCompton KHutchings B(2012)Leveraging latency-insensitivity to ease multiple FPGA designProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145725(175-184)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145725
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An efficient method of partitioning circuits for multiple-FPGA implementation.
1. Hardware

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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

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Tomesh TSaleem ZPerlin MGokhale PSuchara MMartonosi M(2023)Divide and Conquer for Combinatorial Optimization and Distributed Quantum Computation2023 IEEE International Conference on Quantum Computing and Engineering (QCE)10.1109/QCE57702.2023.00009(1-12)Online publication date: 17-Sep-2023
https://doi.org/10.1109/QCE57702.2023.00009
Mao FZhang WFeng BHe BMa YCoskun AMargala MBehjat LHan J(2016)Modular Placement for Interposer based Multi-FPGA SystemsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903025(93-98)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903025
Fleming KAdler MPellauer MParashar AMithal AEmer JCompton KHutchings B(2012)Leveraging latency-insensitivity to ease multiple FPGA designProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145725(175-184)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145725
Bolchini CSandionigi C(2011)A Reliability-Aware Partitioner for Multi-FPGA PlatformsProceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems10.1109/DFT.2011.20(34-40)Online publication date: 3-Oct-2011
https://dl.acm.org/doi/10.1109/DFT.2011.20
Inagi MTakashima YNakamura YKajitani Y(2007)A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/OsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e90-a.5.924E90-A:5(924-931)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1093/ietfec/e90-a.5.924
Liu HWong D(2006)Network-flow-based multiway partitioning with area and pin constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.67363217:1(50-59)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.673632
Fang WWu A(2006)A hierarchical functional structuring and partitioning approach for multiple-FPGA implementationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66268016:10(1188-1195)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.662680
Kim CShin H(2006)A performance-driven logic emulation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50614315:5(560-568)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.506143
Chan PSchlag MZien J(2006)Spectral-based multiway FPGA partitioningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50614215:5(554-560)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.506142
Chou NLiu LCheng CDai WLindelof R(2006)Local ratio cut and set covering partitioning for huge logic emulation systemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.40671014:9(1085-1092)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.406710
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Multiway FPGA partitioning by fully exploiting design hierarchy

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

Multi-FPGA partitioning method based on topological levelization

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Multiway FPGA partitioning by fully exploiting design hierarchy

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

Multi-FPGA partitioning method based on topological levelization

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