research-article

Max registers, counters, and monotone circuits

Authors:

James Aspnes,

Hagit Attiya,

Keren CensorAuthors Info & Claims

PODC '09: Proceedings of the 28th ACM symposium on Principles of distributed computing

Pages 36 - 45

https://doi.org/10.1145/1582716.1582728

Published: 10 August 2009 Publication History

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Abstract

A method is given for constructing a max register, a linearizable, wait-free concurrent data structure that supports a write operation and a read operation that returns the largest value previously written. For fixed m, an m-valued max register can be constructed from one-bit multi-writer multi-reader registers at a cost of at most [lg m] atomic register operations per write or read. The construction takes the form of a binary search tree: applying classic techniques for building unbalanced search trees gives an unbounded max register with cost O(min(log v, n)) to read or write a value v, where n is the number of processes.

It is also shown how a max register can be used to transform any monotone circuit into a wait-free concurrent data structure that provides write operations setting the inputs to the circuit and a read operation that returns the value of the circuit on the largest input values previously supplied. The cost of a write is bounded by O(Sd min([lg m], n), where m is the size of the alphabet for the circuit, S is the number of gates whose value changes as the result of the write, and d is the number of inputs to each gate; the cost of a read is min([lg m], O(n)). While the resulting data structure is not linearizable in general, it satisfies a weaker but natural consistency condition. As an application, we obtain a simple, linearizable, wait-free counter implementation with a cost of O(min(log n log v, n)) to perform an increment and O(min(log v, n)) to perform a read, where v is the current value of the counter. For polynomially-many increments, this becomes O(log² n), an exponential improvement on the best previously known upper bounds of O(n) for an exact counting and O(n^4/5+ε) for approximate counting.

Finally, it is shown that the upper bounds are almost optimal. We prove that min([lg m], n − 1) is a lower bound on the worst-case complexity for any solo-terminating deterministic implementation of an m-valued bounded max register, which is exactly equal to the upper bound for m ≤ 2ⁿ⁻¹. The same bound also holds m-valued counters. Furthermore, even in a solo-terminating randomized implementation of an n-valued max register with an oblivious adversary and global coins, there exist simple schedules containing n − 1 partial write operations and one read operation in which, with high probability, the worst-case step complexity of a read operation is Ω(log n log log n) if the write operations have polylogarithmic step complexity.

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Reviews

Reviewer: Markus Wolf

As processor clock speeds are no longer increasing and performance gains are achieved, more efficient concurrent data structures, with multiple internal threads or multiple cores, are paramount for realizing the possible parallel speedup. This paper describes a novel concurrent implementation of (bounded) max registers that greatly improves the currently known complexity bounds. The method is general enough to be applicable to all problems that can be expressed as monotone circuits. Section 1 starts with a short introduction that presents an overview of the general problem, as well as currently used implementation strategies and complexity results. Section 2 presents the authors' balanced tree-based implementation. Their lemma states: if operations on the subtrees of the recursive tree-based implementation are linearizable, then the complete register is linearizable. The rest of the section establishes the complexity of the implementation and extends the implementation to unbalanced trees and probabilistic implementations. The third section illustrates how max registers can be used to implement monotone circuits: Formally, a monotone circuit computes a function over some finite alphabet of size m , which is assumed to be totally ordered. The circuit is represented by a directed acyclic graph where each node corresponds to a gate that computes a function of the outputs of its predecessors. The authors prove a theorem that states that the implementation is well behaved with respect to concurrent execution of the circuit. The next section presents some natural applications of monotone circuits, such as certain variants of counters and a tagged register. Section 5 establishes lower bounds for the complexity of deterministic and randomized implementations of max registers. These lower bounds show that the given implementation is optimal. Section 6 ends with a discussion of the results and a comparison to other results in the literature. The treatment of the topic is very precise, and understanding it is worthwhile; however, the paper is very densely written and requires some previous knowledge of other results and common implementation techniques. Nevertheless, due to its precision and comprehensiveness, it is accessible to novices who are willing to make an effort. Online Computing Reviews Service

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Published In

PODC '09: Proceedings of the 28th ACM symposium on Principles of distributed computing

August 2009

356 pages

ISBN:9781605583969

DOI:10.1145/1582716

General Chair:
Srikanta Tirthapura
Iowa State University, USA
,
Program Chair:
Lorenzo Alvisi
The University of Texas at Austin, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 August 2009

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PODC '09

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PODC '09: ACM Symposium on Principles of Distributed Computing

August 10 - 12, 2009

AB, Calgary, Canada

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PODC '09 Paper Acceptance Rate 27 of 110 submissions, 25%;

Overall Acceptance Rate 740 of 2,477 submissions, 30%

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Attiya HBender MFarach-Colton MOshman RSchiller NKuznetsov PGelles ROlivetti D(2024)History-Independent Concurrent ObjectsProceedings of the 43rd ACM Symposium on Principles of Distributed Computing10.1145/3662158.3662814(14-24)Online publication date: 17-Jun-2024
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Attiya HCastaneda AEnea CKuznetsov PGelles ROlivetti D(2024)Strong Linearizability using Primitives with Consensus Number 2Proceedings of the 43rd ACM Symposium on Principles of Distributed Computing10.1145/3662158.3662790(432-442)Online publication date: 17-Jun-2024
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Kuznetsov PTonkikh A(2022)Asynchronous reconfiguration with Byzantine failuresDistributed Computing10.1007/s00446-022-00421-135:6(477-502)Online publication date: 10-Mar-2022
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Ovens SMiller ACensor-Hillel K(2021)The Space Complexity of Scannable Binary ObjectsProceedings of the 2021 ACM Symposium on Principles of Distributed Computing10.1145/3465084.3467916(509-519)Online publication date: 21-Jul-2021
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Ovens SWoelfel PRobinson PEllen F(2019)Strongly Linearizable Implementations of Snapshots and Other TypesProceedings of the 2019 ACM Symposium on Principles of Distributed Computing10.1145/3293611.3331632(197-206)Online publication date: 16-Jul-2019
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