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Streaming FFT on REDEFINE-v2: an application-architecture design space exploration

Authors:

Alexander Fell,

Mythri Alle,

Keshavan Varadarajan,

Ranjani NarayanAuthors Info & Claims

CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems

Pages 127 - 136

https://doi.org/10.1145/1629395.1629414

Published: 11 October 2009 Publication History

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Abstract

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC.

For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

References

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Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, and Ranjani Narayan. Generic Routing Rules and a Scalable Access Enhancement for the Network on Chip RECONNECT. In 22nd IEEE International SOC Conference, September 2009.

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Nimmy Joseph, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, and Ranjani Narayan. RECONNECT: A NoC for polymorphic ASICs using a Low Overhead Single Cycle Router. In ASAP '08: Proceedings of the 19th IEEE International Conference on Application specific Systems, Architectures and Processors, July 2008.

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Amar Nath Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, and Ranjani Narayan. REDEFINE: Architecture of a SOC Fabric for Runtime Composition of Computation Structures. In FPL '07: Proceedings of the International Conference on Field Programmable Logic and Applications, August 2007.

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Cited By

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Mahadurkar MMerchant FMaity AVatwani KMunje IGopalan NNandy SNarayan R(2014)Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893215(225-232)Online publication date: Jul-2014
https://doi.org/10.1109/SAMOS.2014.6893215
Madhu KDas SC MS NNandy SNarayan R(2014)Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893214(215-224)Online publication date: Jul-2014
https://doi.org/10.1109/SAMOS.2014.6893214
Krishnamoorthy RVaradarajan KGarga GAlle MNandy SNarayan RFujita MKathail VTatge RBarua R(2010)Towards minimizing execution delays on dynamically reconfigurable processorsProceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1878921.1878935(77-86)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878921.1878935
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Streaming FFT on REDEFINE-v2: an application-architecture design space exploration
1. Computer systems organization
  1. Architectures
    1. Other architectures

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CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems

October 2009

298 pages

ISBN:9781605586267

DOI:10.1145/1629395

Program Chairs:
Joerg Henkel
Karlsruhe University (TH), Germany
,
Sri Parameswaran
University of New South Wales, Australia

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 October 2009

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ESWeek '09: Fifth Embedded Systems Week

October 11 - 16, 2009

Grenoble, France

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Mahadurkar MMerchant FMaity AVatwani KMunje IGopalan NNandy SNarayan R(2014)Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893215(225-232)Online publication date: Jul-2014
https://doi.org/10.1109/SAMOS.2014.6893215
Madhu KDas SC MS NNandy SNarayan R(2014)Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893214(215-224)Online publication date: Jul-2014
https://doi.org/10.1109/SAMOS.2014.6893214
Krishnamoorthy RVaradarajan KGarga GAlle MNandy SNarayan RFujita MKathail VTatge RBarua R(2010)Towards minimizing execution delays on dynamically reconfigurable processorsProceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1878921.1878935(77-86)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878921.1878935
Biswas PUdupa PMondal RVaradarajan KAlle MNandy SNarayan R(2010)Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable PlatformProceedings of the 2010 IEEE Annual Symposium on VLSI10.1109/ISVLSI.2010.65(161-166)Online publication date: 5-Jul-2010
https://dl.acm.org/doi/10.1109/ISVLSI.2010.65
Biswas PVaradarajan KAlle MNandy SNarayan R(2010)Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation10.1109/ICSAMOS.2010.5642058(265-272)Online publication date: Jul-2010
https://doi.org/10.1109/ICSAMOS.2010.5642058

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REDEFINE: Runtime reconfigurable polymorphic ASIC

A dynamically reconfigurable communication architecture for multicore embedded systems

Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration

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REDEFINE: Runtime reconfigurable polymorphic ASIC

A dynamically reconfigurable communication architecture for multicore embedded systems

Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration

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