Empirical study of latency hiding on a fine-grain parallel processor
Authors: 
Kei Hiraki, Toshio Shimada, and Satoshi SekiguchiAuthors Info & Claims
Kei Hiraki, Toshio Shimada, and Satoshi SekiguchiAuthors Info & ClaimsAugust 1993
Pages 220 - 229
Abstract
Latency associated with memory accesses and process communications are one of the most difficult obstacles in constructing a practical massively parallel system. So far, two approaches to hide latencies have been proposed. They are prefetching and multi-threading. An instruction-level data-driven computer is an ideal test-bed for evaluating these latency hiding methods because prefetching and multi-threading are naturally implemented in an instruction-level data-driven computer as unfolding and concurrent execution of multiple contexts. This paper evaluates latency hiding methods on SIGMA-1, a dataflow supercomputer developed in Electrotechnical Laboratory. As a result of evaluation, these methods are effective to hide static latencies but not effective to hide dynamic latencies. Also, concurrent execution of multiple contexts is more effective than prefetching.
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- Empirical study of latency hiding on a fine-grain parallel processor
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Published: 01 August 1993
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