research-article

Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing

Authors:

Alan D. George,

Rafael GarciaAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 3, Issue 1

Article No.: 5, Pages 1 - 23

https://doi.org/10.1145/1661438.1661443

Published: 01 January 2010 Publication History

Abstract

High-Level Languages (HLLs) for Field-Programmable Gate Arrays (FPGAs) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, programming at a higher level of abstraction is typically accompanied by some loss of performance as well as reduced transparency of application behavior, making it difficult to understand and improve application performance. While runtime tools for performance analysis are often featured in development with traditional HLLs for sequential and parallel programming, HLL-based development for FPGAs has an equal or greater need yet lacks these tools. This article presents a novel and portable framework for runtime performance analysis of HLL applications for FPGAs, including an automated tool for performance analysis of designs created with Impulse C, a commercial HLL for FPGAs. As a case study, this tool is used to successfully locate performance bottlenecks in a molecular dynamics kernel in order to gain speedup.

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Cited By

Lai YUstun EXiang SFang ZRong HZhang Z(2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
https://dl.acm.org/doi/10.1145/3469660
Yasudo RCoutinho JVarbanescu ALuk WAmano HBecker TGuo C(2021)Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow PlatformsACM Transactions on Reconfigurable Technology and Systems10.1145/345274214:3(1-21)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3452742
Huthmann JPodobas ASommer LKoch ASano K(2020)Extending High-Level Synthesis with High-Performance Computing Performance Visualization2020 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER49012.2020.00047(371-380)Online publication date: Sep-2020
https://doi.org/10.1109/CLUSTER49012.2020.00047
Show More Cited By

Index Terms

Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
1. Hardware
  1. Hardware validation

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 3, Issue 1

January 2010

136 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/1661438

Issue’s Table of Contents

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 2010

Accepted: 01 April 2009

Revised: 01 November 2008

Received: 01 July 2008

Published in TRETS Volume 3, Issue 1

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Cited By

Lai YUstun EXiang SFang ZRong HZhang Z(2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
https://dl.acm.org/doi/10.1145/3469660
Yasudo RCoutinho JVarbanescu ALuk WAmano HBecker TGuo C(2021)Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow PlatformsACM Transactions on Reconfigurable Technology and Systems10.1145/345274214:3(1-21)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3452742
Huthmann JPodobas ASommer LKoch ASano K(2020)Extending High-Level Synthesis with High-Performance Computing Performance Visualization2020 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER49012.2020.00047(371-380)Online publication date: Sep-2020
https://doi.org/10.1109/CLUSTER49012.2020.00047
Ruiz-Rosero JRamirez-Gonzalez GKhanna R(2019)Field Programmable Gate Array Applications—A Scientometric ReviewComputation10.3390/computation70400637:4(63)Online publication date: 11-Nov-2019
https://doi.org/10.3390/computation7040063
Hu NZhou XLi XWang C(2018)3D Waveform Oscilloscope Implemented on Coupled FPGA-GPU Embedded System2018 5th International Conference on Information Science and Control Engineering (ICISCE)10.1109/ICISCE.2018.00010(1-5)Online publication date: Jul-2018
https://doi.org/10.1109/ICISCE.2018.00010
Wang ZHe BZhang WJiang S(2016)A performance analysis framework for optimizing OpenCL applications on FPGAs2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446058(114-125)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446058
Colodro-Conde CToledo-Moreo FToledo-Moreo RMartínez-Álvarez JGarrigós-Guerrero JFerrández-Vicente J(2014)A practical evaluation of the performance of the Impulse CoDeveloper HLS tool for implementing large-kernel 2-D filtersJournal of Real-Time Image Processing10.1007/s11554-013-0374-x9:1(263-279)Online publication date: 1-Mar-2014
https://dl.acm.org/doi/10.1007/s11554-013-0374-x
da Silva BBraeken AD'Hollander ETouhafi A(2013)Performance modeling for FPGAsInternational Journal of Reconfigurable Computing10.1155/2013/4280782013(7-7)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1155/2013/428078
Castells-Rufas DFernandez-Alonso ECarrabina J(2012)Performance analysis techniques for multi-soft-core and many-soft-core systemsInternational Journal of Reconfigurable Computing10.1155/2012/7363472012(2-2)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/736347
Curreri JStitt GGeorge ACompton KHutchings B(2012)Communication visualization for bottleneck detection of high-level synthesis applicationsProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145701(33-36)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145701
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