Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/1669112.1669117acmconferencesArticle/Chapter ViewAbstractPublication PagesmicroConference Proceedingsconference-collections
research-article

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

Published: 12 December 2009 Publication History

Abstract

Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure only a maximum of 107 - 108 writes, making a PCM based system have a lifetime of only a few years under ideal conditions. Furthermore, we show that non-uniformity in writes to different cells reduces the achievable lifetime of PCM system by 20x. Writes to PCM cells can be made uniform with Wear-Leveling. Unfortunately, existing wear-leveling techniques require large storage tables and indirection, resulting in significant area and latency overheads.
We propose Start-Gap, a simple, novel, and effective wear-leveling technique that uses only two registers. By combining Start-Gap with simple address-space randomization techniques we show that the achievable lifetime of the baseline 16GB PCM-based system is boosted from 5% (with no wear-leveling) to 97% of the theoretical maximum, while incurring a total storage overhead of less than 13 bytes and obviating the latency overhead of accessing large tables.
We also analyze the security vulnerabilities for memory systems that have limited write endurance, showing that under adversarial settings, a PCM-based system can fail in less than one minute. We provide a simple extension to Start-Gap that makes PCM-based systems robust to such malicious attacks.

References

[1]
International Technology Roadmap for Semiconductors, ITRS 2007.
[2]
A. Ban and R. Hasharon. Wear leveling of static areas in flash memory. U.S. Patent Number 6,732,221, 2004.
[3]
A. Ben-Aroya and S. Toledo. Competitive analysis of flash-memory algorithms. In ESA'06: Proceedings of the 14th conference on Annual European Symposium, pages 100--111, 2006.
[4]
F. J. Corbato. A paging experiment with the multics system. MIT project MAC Report MAC-M-384, May 1968.
[5]
R. Freitas and W. Wilcke. Storage-class memory: The next storage system technology. IBM Journal of R. and D., 52(4/5):439--447, 2008.
[6]
E. Gal and S. Toledo. Algorithms and data structures for flash memories. ACM Comput. Surv., 37(2):138--163, 2005.
[7]
T. Kgil, D. Roberts, and T. Mudge. Improving nand flash based disk caches. In ISCA '08: Proceedings of the 35th annual international symposium on Computer architecture, pages 327--338, 2008.
[8]
B. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. In ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture, 2009.
[9]
C. Lefurgy et al. Energy management for commercial servers. IEEE Computer, 36(12):39--48, Dec. 2003.
[10]
A. A. Liddicoat and M. J. Flynn. Parallel square and cube computations. In IEEE 34th Asilomar Confernce on Signals, Systems and Computers, 2000.
[11]
M. Luby and C. Rackoff. How to construct pseudorandom permutations from pseudorandom functions. SIAM J. Comput., 17(2):373--386, 1988.
[12]
M-Systems. TrueFFS Wear-leveling Mechanism. http://www.dataio.com/pdf/NAND/MSystems/TrueFFS_Wear_Leveling_Mechanism.pdf.
[13]
A. J. Menezes, P. C. van Oorschot, and S. A. Vanstone. Handbook of Applied Cryptography. 1996.
[14]
T. Moscibroda and O. Mutlu. Memory performance attacks: denial of memory service in multi-core systems. In SS'07: Proceedings of 16th USENIX Security Symposium, 2007.
[15]
M. Qureshi, V. Srinivasan, and J. Rivers. Scalable high performance main memory system using phase-change memory technology. In ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture, 2009.
[16]
S. Raoux et al. Phase-change random access memory: A scalable technology. IBM Journal of R. and D., 52(4/5):465--479, 2008.
[17]
S. Ross. A First Course in Probability. Pearson Prentice Hall, 2006.
[18]
J. Shin, V. Zyuban, P. Bose, and T. M. Pinkston. A proactive wearout recovery approach for exploiting microarchitectural redundancy to extend cache sram lifetime. In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, pages 353--362, 2008.
[19]
J. Tominaga, T. Kikukawa, M. Takahashi, and R. T. Phillips. Structure of the Optical Phase Change Memory Alloy, AgVInSbTe, Determined by Optical Spectroscopy and Electron Diffraction,. J. Appl. Phys., 82(7), 1997.
[20]
N. Yamada et al. Rapid-Phase Transitions of GeTe-Sb2Te3 Pseudobinary Amorphous Thin Films for an Optical Disk Memory. J. Appl. Phys., 69(5), 1991.
[21]
P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture, 2009.

Cited By

View all
  • (2024)AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main MemoriesACM Transactions on Design Automation of Electronic Systems10.1145/368933429:6(1-24)Online publication date: 20-Aug-2024
  • (2024)MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and EnduranceProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676890(26-39)Online publication date: 14-Oct-2024
  • (2024)A Scalable Wear Leveling Technique for Phase Change MemoryACM Transactions on Storage10.1145/363114620:1(1-26)Online publication date: 30-Jan-2024
  • Show More Cited By

Index Terms

  1. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
    December 2009
    601 pages
    ISBN:9781605587981
    DOI:10.1145/1669112
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 12 December 2009

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. endurance
    2. phase change memory
    3. wear leveling

    Qualifiers

    • Research-article

    Conference

    Micro-42
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 484 of 2,242 submissions, 22%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)80
    • Downloads (Last 6 weeks)9
    Reflects downloads up to 23 Dec 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main MemoriesACM Transactions on Design Automation of Electronic Systems10.1145/368933429:6(1-24)Online publication date: 20-Aug-2024
    • (2024)MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and EnduranceProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676890(26-39)Online publication date: 14-Oct-2024
    • (2024)A Scalable Wear Leveling Technique for Phase Change MemoryACM Transactions on Storage10.1145/363114620:1(1-26)Online publication date: 30-Jan-2024
    • (2024)Rubix: Reducing the Overhead of Secure Rowhammer Mitigations via Randomized Line-to-Row MappingProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640404(1014-1028)Online publication date: 27-Apr-2024
    • (2024)Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence DomainACM Transactions on Embedded Computing Systems10.1145/360747323:6(1-34)Online publication date: 11-Sep-2024
    • (2024)I/O Causality Based In-Line Data Deduplication for Non-Volatile Memory Enabled Storage SystemsIEEE Transactions on Computers10.1109/TC.2024.336596173:5(1327-1340)Online publication date: May-2024
    • (2024)DRCTL: A Disorder-Resistant Computation Translation Layer Enhancing the Lifetime and Performance of Memristive CIM Architecture2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00028(263-277)Online publication date: 2-Nov-2024
    • (2024)Compiler-Directed Whole-System Persistence2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00074(961-977)Online publication date: 29-Jun-2024
    • (2024)CaitiJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2024.103109150:COnline publication date: 1-May-2024
    • (2024)Ensuring consistent recovery under power failure with minimal NVM write overheadJournal of Systems Architecture10.1016/j.sysarc.2024.103083148(103083)Online publication date: Mar-2024
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media