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Flexible architectural support for fine-grain scheduling

Published: 13 March 2010 Publication History

Abstract

To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is particularly challenging, as the runtime must ensure load balance without compromising locality and introducing small overheads. Software-only schedulers can implement various scheduling algorithms that match the characteristics of different applications and programming models, but suffer significant overheads as they synchronize and communicate task information over the deep cache hierarchy of a large-scale CMP. To reduce these costs, hardware-only schedulers like Carbon, which implement task queuing and scheduling in hardware, have been proposed. However, a hardware-only solution fixes the scheduling algorithm and leaves no room for other uses of the custom hardware.
This paper presents a combined hardware-software approach to build fine-grain schedulers that retain the flexibility of software schedulers while being as fast and scalable as hardware ones. We propose asynchronous direct messages (ADM), a simple architectural extension that provides direct exchange of asynchronous, short messages between threads in the CMP without going through the memory hierarchy. ADM is sufficient to implement a family of novel, software-mostly schedulers that rely on low-overhead messaging to efficiently coordinate scheduling and transfer task information. These schedulers match and often exceed the performance and scalability of Carbon when using the same scheduling algorithm. When the ADM runtime tailors its scheduling algorithm to application characteristics, it outperforms Carbon by up to 70%.

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Published In

cover image ACM Conferences
ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems
March 2010
422 pages
ISBN:9781605588391
DOI:10.1145/1736020
  • General Chair:
  • James C. Hoe,
  • Program Chair:
  • Vikram S. Adve
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 45, Issue 3
    ASPLOS '10
    March 2010
    399 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/1735971
    Issue’s Table of Contents
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 38, Issue 1
    ASPLOS '10
    March 2010
    399 pages
    ISSN:0163-5964
    DOI:10.1145/1735970
    Issue’s Table of Contents
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Published: 13 March 2010

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Author Tags

  1. chip-multiprocessors
  2. fine-grain scheduling
  3. many-core
  4. messaging
  5. scheduling
  6. work-stealing

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ASPLOS XV Paper Acceptance Rate 32 of 181 submissions, 18%;
Overall Acceptance Rate 535 of 2,713 submissions, 20%

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  • (2023)μManycore: A Cloud-Native CPU for Tail at ScaleProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589068(1-15)Online publication date: 17-Jun-2023
  • (2023)Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline Parallelism2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071026(1262-1274)Online publication date: Feb-2023
  • (2021)A case against (most) context switchesProceedings of the Workshop on Hot Topics in Operating Systems10.1145/3458336.3465274(17-25)Online publication date: 1-Jun-2021
  • (2021)CacheInspectorACM Transactions on Architecture and Code Optimization10.1145/345737318:3(1-25)Online publication date: 8-Jun-2021
  • (2021)GraphPEGACM Transactions on Architecture and Code Optimization10.1145/345044018:3(1-24)Online publication date: 10-May-2021
  • (2021)Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in MulticoresIEEE Computer Architecture Letters10.1109/LCA.2020.304567020:1(17-21)Online publication date: 1-Jan-2021
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  • (2020)Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA45697.2020.00025(173-186)Online publication date: May-2020
  • (2020)DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-020-00687-7Online publication date: 20-Nov-2020
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