research-article

Modeling shared cache and bus in multi-cores for timing analysis

Authors:

Sudipta Chattopadhyay,

Abhik Roychoudhury,

Tulika MitraAuthors Info & Claims

SCOPES '10: Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems

Article No.: 6, Pages 1 - 10

https://doi.org/10.1145/1811212.1811220

Published: 28 June 2010 Publication History

Abstract

Timing analysis of concurrent programs running on multi-core platforms is currently an important problem. The key to solving this problem is to accurately model the timing effects of shared resources in multi-cores, namely shared cache and bus. In this paper, we provide an integrated timing analysis framework that captures timing effects of both shared cache and shared bus. We also develop a cycle-accurate simulation infra-structure to evaluate the precision of our analysis. Experimental results from a large fragment of an in-orbit spacecraft software show that our analysis produces around 20% over-estimation over simulation results.

References

[1]

S. Baldawa and R. Sangireddy. CMP-SIM: an environment for simulating chip multiprocessor (cmp) architectures. http://www.utdallas.edu/~rama.sangireddy/CMP-SIM.

[2]

T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. Computer, 2002.

Digital Library

[3]

European Space Agency. DEBIE -- First standard space debris monitoring instrument, 2008. Available at: http://gate.etamax.de/edid/publicaccess/debie1.php.

[4]

ARM. ARM Cortex-A9 MPCore processor. http://www.arm.com/pdfs/ARMCortexA-9Processors.pdf.

[5]

G. Varghese et al. Penryn: 45-nm next generation Intel core-2 processor. In IEEE Asian Solid-State Circuits Conf., 2007.

[6]

S. Tam Rusu et al. A 65-nm Dual-Core Multithreaded Xeon processor with 16-MB L3 Cache. IEEE Journal Of Solid State Circuits, (1), 2007.

[7]

D. Hardy and I. Puaut. WCET analysis of multi-level non-inclusive set-associative instruction caches. In RTSS, 2008.

Digital Library

[8]

H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and precise wcet prediction by separated cache and path analyses. Real-Time Systems, 18:157--179, 2000.

Digital Library

[9]

Y. Li et al. Timing analysis of concurrent programs running on shared cache multi cores. In RTSS, 2009.

Digital Library

[10]

WCET benchmarks. http://www.mrtc.mdh.se/projects/wcet/benchmarks.html.

[11]

Intel. Intel Core-2 Duo Processor. http://www.intel.com/products/processor/core2duo/index.htm.

[12]

C.-G. Lee et al. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Transactions on Computers, 47(6):700--713, 1998.

Digital Library

[13]

H. S. Negi, T. Mitra, and A. Roychoudhury. Accurate estimation of cache-related preemption delay. In CODES-ISSS, 2003.

Digital Library

[14]

S. Schliecker et al. Reliable performance analysis of a multicore multithreaded system-on-chip. In CODES-ISSS, 2008.

Digital Library

[15]

J. W. Lee and K. Asanovic. METERG: Measurement-based end-to-end performance estimation technique in QoS-capable multiprocessors. In RTAS, 2006.

Digital Library

[16]

J. Yan and W. Zhang. WCET analysis for multi-core processors with shared L2 instruction caches. In RTAS, 2008.

Digital Library

[17]

D. Hardy, T. Piquet, and I. Puaut. Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In RTSS, 2009.

Digital Library

[18]

H. Kopetz. Real-time Systems Design Principles for Distributed Embedded Applications. Kluwer, 1999.

Digital Library

[19]

K. Tindell and J. Clark. Holistic schedulability for distributed hard real-time systems. Microprocessing & Microprogramming, 50(2--3), 1994.

Digital Library

[20]

J. Rosen et al. Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In RTSS, 2007.

Digital Library

[21]

M. Paolieri et al. Hardware support for WCET analysis of hard real-time multicore systems. In ISCA, 2009.

Digital Library

Cited By

Farina GGala GCinque MFohler G(2022)Assessing Intel’s Memory Bandwidth Allocation for resource limitation in real-time systems2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)10.1109/ISORC52572.2022.9812757(1-8)Online publication date: 17-May-2022
https://doi.org/10.1109/ISORC52572.2022.9812757
Arora JMaia CRashid SNelissen GTovar E(2022)Schedulability analysis for 3-phase tasks with partitioned fixed-priority schedulingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102706131:COnline publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1016/j.sysarc.2022.102706
Arora JMaia CRashid SNelissen GTovar E(2022)Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration schemeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102345122:COnline publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102345
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Index Terms

Modeling shared cache and bus in multi-cores for timing analysis
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Published In

cover image ACM Other conferences

SCOPES '10: Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems

June 2010

91 pages

ISBN:9781450300841

DOI:10.1145/1811212

General Chair:
Ed Deprettere
Leiden University, NL
,
Program Chair:
Todor Stefanov
Leiden University, NL

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAA: European Design Automation Association

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 June 2010

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National University of Singapore

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SCOPES '10

Sponsor:

EDAA

SCOPES '10: 13th International Workshop on Software and Compilers for Embedded Systems

June 28 - 29, 2010

St. Goar, Germany

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Overall Acceptance Rate 38 of 79 submissions, 48%

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Cited By

Farina GGala GCinque MFohler G(2022)Assessing Intel’s Memory Bandwidth Allocation for resource limitation in real-time systems2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)10.1109/ISORC52572.2022.9812757(1-8)Online publication date: 17-May-2022
https://doi.org/10.1109/ISORC52572.2022.9812757
Arora JMaia CRashid SNelissen GTovar E(2022)Schedulability analysis for 3-phase tasks with partitioned fixed-priority schedulingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102706131:COnline publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1016/j.sysarc.2022.102706
Arora JMaia CRashid SNelissen GTovar E(2022)Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration schemeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102345122:COnline publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102345
Arora JMaia CAftab Rashid SNelissen GTovar E(2021)Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned SchedulingProceedings of the 29th International Conference on Real-Time Networks and Systems10.1145/3453417.3453433(123-133)Online publication date: 7-Apr-2021
https://dl.acm.org/doi/10.1145/3453417.3453433
Rashid SNelissen GTovar E(2020)Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116265(442-447)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116265
Nguyen VHardy DPuaut I(2019)Cache-conscious off-line real-time scheduling for multi-core platforms: algorithms and implementationReal-Time Systems10.1007/s11241-019-09333-zOnline publication date: 6-Mar-2019
https://doi.org/10.1007/s11241-019-09333-z
Xing HZhou JSong XQi R(2018)A Dynamic Multi-Objective Evolutionary Algorithm for Nontrivial Upper Bounds of Real-Time Tasks in Embedded System Design2018 IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced & Trusted Computing, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI)10.1109/SmartWorld.2018.00082(277-286)Online publication date: Oct-2018
https://doi.org/10.1109/SmartWorld.2018.00082
Xing HZhou JSong XQi R(2018)SMT-Based Timing Analysis and Verification of Real-Time Task2018 IEEE 42nd Annual Computer Software and Applications Conference (COMPSAC)10.1109/COMPSAC.2018.00106(711-720)Online publication date: Jul-2018
https://doi.org/10.1109/COMPSAC.2018.00106
Davis RAltmeyer SIndrusiak LMaiza CNelis VReineke J(2018)An extensible framework for multicore response time analysisReal-Time Systems10.1007/s11241-017-9285-454:3(607-661)Online publication date: 1-Jul-2018
https://dl.acm.org/doi/10.1007/s11241-017-9285-4
Kedar GMendelson ACidon I(2017)SPACEIEEE Transactions on Computers10.1109/TC.2016.260877566:4(717-730)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TC.2016.2608775
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