research-article

Non-uniform clock mesh optimization with linear programming buffer insertion

Authors:

Matthew R. Guthaus,

Ricardo ReisAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 74 - 79

https://doi.org/10.1145/1837274.1837295

Published: 13 June 2010 Publication History

Abstract

Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. However, this robustness costs power. In this work, we present a mesh edge displacement algorithm that is able to reduce mesh wire length by 7.6% and overall power by 10.5% with a small mean skew improvement. We also present the first non-greedy buffer placement and sizing technique using linear programming (LP) and iterative buffer removal. We show that compared to prior methods, we can obtain 41% power reduction and an 27ps mean skew reduction on average when variation is considered compared to prior algorithms.

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Cited By

Li DGan JShen CChen QYang LQiu SJin XWu TChen ZLiu M(2024)Clock mesh synthesis through dynamic programming with physical parameters considerationIntegration10.1016/j.vlsi.2024.102261(102261)Online publication date: Aug-2024
https://doi.org/10.1016/j.vlsi.2024.102261
Cheng WYeh ZKao HHuang S(2023)Cross-Mesh Clock Network SynthesisElectronics10.3390/electronics1216341012:16(3410)Online publication date: 11-Aug-2023
https://doi.org/10.3390/electronics12163410
Kwon TImran MPan DYang J(2020)Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.296691228:5(1256-1268)Online publication date: May-2020
https://doi.org/10.1109/TVLSI.2020.2966912
Show More Cited By

Index Terms

Non-uniform clock mesh optimization with linear programming buffer insertion
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

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Published: 13 June 2010

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DAC '10

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Li DGan JShen CChen QYang LQiu SJin XWu TChen ZLiu M(2024)Clock mesh synthesis through dynamic programming with physical parameters considerationIntegration10.1016/j.vlsi.2024.102261(102261)Online publication date: Aug-2024
https://doi.org/10.1016/j.vlsi.2024.102261
Cheng WYeh ZKao HHuang S(2023)Cross-Mesh Clock Network SynthesisElectronics10.3390/electronics1216341012:16(3410)Online publication date: 11-Aug-2023
https://doi.org/10.3390/electronics12163410
Kwon TImran MPan DYang J(2020)Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.296691228:5(1256-1268)Online publication date: May-2020
https://doi.org/10.1109/TVLSI.2020.2966912
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889756
Chou CLai YChang YWang CCheng LHuang SChang S(2017)Ping-Pong MeshIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256520236:1(146-155)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2565202
CHENG WHUNG JCHIU Y(2016)Non-Uniform Clock Mesh Synthesis with Clock Gating and Register ClusteringIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E99.A.2388E99.A:12(2388-2397)Online publication date: 2016
https://doi.org/10.1587/transfun.E99.A.2388
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Jung JLee DShin Y(2015)Design and Optimization of Multiple-Mesh Clock NetworkVLSI-SoC: Internet of Things Foundations10.1007/978-3-319-25279-7_3(39-57)Online publication date: 25-Nov-2015
https://doi.org/10.1007/978-3-319-25279-7_3
Cho KJang CChong J(2014)Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated CircuitsETRI Journal10.4218/etrij.14.0113.125736:6(931-941)Online publication date: 1-Dec-2014
https://doi.org/10.4218/etrij.14.0113.1257
Suresh VBurleson W(2014)Variation Aware Design of Post-Silicon Tunable Clock BufferProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.95(1-6)Online publication date: 9-Jul-2014
https://dl.acm.org/doi/10.1109/ISVLSI.2014.95
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