research-article

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Authors:

Jonathan A. Winter,

David H. Albonesi,

Christine A. ShoemakerAuthors Info & Claims

PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniques

Pages 29 - 40

https://doi.org/10.1145/1854273.1854283

Published: 11 September 2010 Publication History

Abstract

Future many-core microprocessors are likely to be heterogeneous, by design or due to variability and defects. The latter type of heterogeneity is especially challenging due to its unpredictability. To minimize the performance and power impact of these hardware imperfections, the runtime thread scheduler and global power manager must be nimble enough to handle such random heterogeneity. With hundreds of cores expected on a single die in the future, these algorithms must provide high power-performance efficiency, yet remain scalable with low runtime overhead.

This paper presents a range of scheduling and power management algorithms and performs a detailed evaluation of their effectiveness and scalability on heterogeneous many-core architectures with up to 256 cores. We also conduct a limit study on the potential benefits of coordinating scheduling and power management and demonstrate that coordination yields little benefit. We highlight the scalability limitations of previously proposed thread scheduling algorithms that were designed for small-scale chip multiprocessors and propose a Hierarchical Hungarian Scheduling Algorithm that dramatically reduces the scheduling overhead without loss of accuracy. Finally, we show that the high computational requirements of prior global power management algorithms based on linear programming make them infeasible for many-core chips, and that an algorithm that we call Steepest Drop achieves orders of magnitude lower execution time without sacrificing power-performance efficiency.

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Scalable thread scheduling and global power management for heterogeneous many-core architectures

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cover image ACM Conferences

PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniques

September 2010

596 pages

ISBN:9781450301787

DOI:10.1145/1854273

General Chair:
Valentina Salapura
IBM TJ Watson Research Center
,
Program Chairs:
Michael Gschwind
IBM Systems & Technology Group
,
Jens Knoop
Technische Universität Wien

Copyright © 2010 ACM.

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IFIP WG 10.3: IFIP working group 10.3 on concurrent systems
IEEE CS TCPP: IEEE-CS technical committee on parallel processing
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IEEE CS TCAA: IEEE CS technical committee on architectural acoustics

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Association for Computing Machinery

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Published: 11 September 2010

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PACT '10: International Conference on Parallel Architectures and Compilation Techniques

September 11 - 15, 2010

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https://dl.acm.org/doi/10.1145/3581784.3607055
Zou AMa YGarimella KLee BGill CZhang X(2023)F-LEMMA: Fast Learning-Based Energy Management for Multi-/Many-Core ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317621942:2(616-629)Online publication date: Feb-2023
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