Article

Free access

Digital receiver design using VHDL generation from data flow graphs

Authors:

Peter Zepter,

Thorsten Grötker,

Heinrich MeyrAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 228 - 233

https://doi.org/10.1145/217474.217534

Published: 01 January 1995 Publication History

PDF eReader

References

[1]

G. Jennings, "A case against event driven simulation of digital system design," in The 24th Annual Simulation Symposium, pp. 170-176, IEEE Computer Society Press, April 1991.

Digital Library

Google Scholar

[2]

O.J. Joeressen, G. Schneider, and H. Meyr, "Systematic Design Optimization of a Competitive Soft-Concatenated Decoding System," in VLSI Signal Processing 6 (L. Eggermont et al., ed.), pp. 105-113, IEEE, 1993.

Google Scholar

[3]

Cadence Design Systems, 919 E. Hillsdale Blvd., Foster City, CA 94404, USA, SPW User's Manual.

Google Scholar

[4]

P.B. Tjahjadi, P. T. Yang, B. C. Wong, B.-Y. Chung, E. G. Cohen, and R. Jain, "Vanda- a CAD system for communication signal processing circuits design," in VLSI Signal Processing IV, ch. 5, IEEE Press, 1990.

Google Scholar

[5]

Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA, COSSAP User's Manual.

Google Scholar

[6]

E.A. Lee, "Consistency in dataflow graphs," IEEE Trans. on Parallel and Distr. Systems, vol. 2, pp. 223-235, Apr. 1991.

Digital Library

Google Scholar

[7]

J.T. Buck and E. A. Lee, "Scheduling dynamic dataflow graphs with bounded memory using the token flow model," in Proc. ICASSP'93, pp. 1-429-I-432, IEEE, 1993.

Google Scholar

[8]

T. Murata, "Petri nets: Properties, analysis and applications," Proc. of the IEEE, vol. 77, pp. 541-580, April 1989.

Crossref

Google Scholar

[9]

E.A. Lee and D. G. Messerschmitt, "Static scheduling of synchronous data flow programs for digital signal processing," IEEE Trans. on Computers, vol. 36, pp. 24-35, Jan. 1987.

Digital Library

Google Scholar

[10]

H. V. Jagadisch and T. Kailath, "Obtaining schedules for digital systems," IEEE Trans. on Signal Processing, vol. 39, pp. 2296- 2316, Oct. 1991.

Digital Library

Google Scholar

[11]

C. E. Leiserson, F. Rose, and J. Saxe, "Optimizing synchronous circuitry for retiming," in Proc. of the 3rd CaItech Conf. on VLSI, (Pasadena), pp. 87-116, March 1983.

Google Scholar

[12]

U. Lambrette and H. Meyr, "Two timing recovery algorithms for MSK," in Intl. Conf. on Comm., 1994.

Google Scholar

[13]

Texas Instruments, FPGA Data Manual.

Google Scholar

Cited By

View all

Tripakis SAndrade HGhosal ALimaye RRavindran KWang GYang GKormerup JWong IDick RMadsen J(2011)Correct and non-defensive glue design using abstract modelsProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039382(59-68)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1145/2039370.2039382
Jung HYang HHa S(2008)Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW CosynthesisJournal of Signal Processing Systems10.1007/s11265-007-0070-952:1(13-34)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1007/s11265-007-0070-9
Jung HHa SOrailoglu AChou PEles PJantsch A(2004)Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesisProceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1016720.1016730(24-29)Online publication date: 8-Sep-2004
https://dl.acm.org/doi/10.1145/1016720.1016730
Show More Cited By

Index Terms

Digital receiver design using VHDL generation from data flow graphs
1. Hardware

Recommendations

Comments

Information & Contributors

Information

Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1995

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC95

Sponsor:

EDAC
SIGDA

DAC95: The 32nd Design Automation Conference

June 12 - 16, 1995

California, San Francisco, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

28
Total Citations
View Citations
912
Total Downloads

Downloads (Last 12 months)51
Downloads (Last 6 weeks)5

Reflects downloads up to 10 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Tripakis SAndrade HGhosal ALimaye RRavindran KWang GYang GKormerup JWong IDick RMadsen J(2011)Correct and non-defensive glue design using abstract modelsProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039382(59-68)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1145/2039370.2039382
Jung HYang HHa S(2008)Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW CosynthesisJournal of Signal Processing Systems10.1007/s11265-007-0070-952:1(13-34)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1007/s11265-007-0070-9
Jung HHa SOrailoglu AChou PEles PJantsch A(2004)Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesisProceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1016720.1016730(24-29)Online publication date: 8-Sep-2004
https://dl.acm.org/doi/10.1145/1016720.1016730
Mc Allister JWoods RWalke R(2004)Embedded Context Aware Hardware Component Generation for Dataflow System ExplorationComputer Systems: Architectures, Modeling, and Simulation10.1007/978-3-540-27776-7_27(254-263)Online publication date: 2004
https://doi.org/10.1007/978-3-540-27776-7_27
Jung HLee KHa S(2002)Efficient hardware controller synthesis for synchronous dataflow graph in system level designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80776510:4(423-428)Online publication date: 1-Aug-2002
https://dl.acm.org/doi/10.1109/TVLSI.2002.807765
Park CKim SHa SGoto S(2001)A dataflow specification for system level synthesis of 3D graphics applicationsProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370282(78-84)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370282
Chanik Park Sungchan Kim Soonhoi Ha (2001)Dataflow specification for system level synthesis of 3D graphics applicationsProceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)10.1109/ASPDAC.2001.913284(78-83)Online publication date: 2001
https://doi.org/10.1109/ASPDAC.2001.913284
Park CHa SKurdahi FHermida R(2000)Hardware synthesis from SPDF representation for multimedia applicationsProceedings of the 13th international symposium on System synthesis10.5555/501790.501835(215-220)Online publication date: 20-Sep-2000
https://dl.acm.org/doi/10.5555/501790.501835
Jung HLee KHa SKurdahi FHermida R(2000)Efficient hardware controller synthesis for synchronous dataflow graph in system level designProceedings of the 13th international symposium on System synthesis10.5555/501790.501810(79-84)Online publication date: 20-Sep-2000
https://dl.acm.org/doi/10.5555/501790.501810
Horstmannshoff JMeyr HDe Micheli G(2000)Efficient building block based RTL code generation from synchronous data flow graphsProceedings of the 37th Annual Design Automation Conference10.1145/337292.337576(552-555)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337576
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Digital Systems Design Using VHDL

Redes de petri e VHDL na especificação de controladores paralelos / Petri Nets and VHDL in the Parallel Controllers Specification

Extensões Para Design de Hardware Digital Em Aplicações Aeroespaciais

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Index Terms

Recommendations

Digital Systems Design Using VHDL

Redes de petri e VHDL na especificação de controladores paralelos / Petri Nets and VHDL in the Parallel Controllers Specification

Extensões Para Design de Hardware Digital Em Aplicações Aeroespaciais

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations