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Orthogonal greedy coupling: a new optimization approach to 2-D FPGA routing

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Yu-Liang Wu,

Malgorzata Marek-SadowskaAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 568 - 573

https://doi.org/10.1145/217474.217591

Published: 01 January 1995 Publication History

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Eum NKim TKyung C(2004)CeRAIEEE Transactions on Computers10.1109/TC.2004.2053:7(829-842)Online publication date: 1-Jul-2004
https://dl.acm.org/doi/10.1109/TC.2004.20
Lin JPan SChang YYasuura H(2003)Graph matching-based algorithms for array-based FPGA segmentation design and routingProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119959(851-854)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119959
Eum NKim TKyung CErnst R(2001)A router for symmetrical FPGAs based on exact routing density evaluationProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603123(137-143)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603123
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Orthogonal greedy coupling: a new optimization approach to 2-D FPGA routing
1. Hardware

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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

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Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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Eum NKim TKyung C(2004)CeRAIEEE Transactions on Computers10.1109/TC.2004.2053:7(829-842)Online publication date: 1-Jul-2004
https://dl.acm.org/doi/10.1109/TC.2004.20
Lin JPan SChang YYasuura H(2003)Graph matching-based algorithms for array-based FPGA segmentation design and routingProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119959(851-854)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119959
Eum NKim TKyung CErnst R(2001)A router for symmetrical FPGAs based on exact routing density evaluationProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603123(137-143)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603123
Lee KWong MHauck S(2001)LRouteProceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays10.1145/360276.360290(12-20)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1145/360276.360290
Karro JCohoon J(2001)Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-ArraysField-Programmable Logic and Applications10.1007/3-540-44687-7_26(243-253)Online publication date: 17-Aug-2001
https://doi.org/10.1007/3-540-44687-7_26
Chang YChang YDe Micheli G(2000)An architecture-driven metric for simultaneous placement and global routing for FPGAsProceedings of the 37th Annual Design Automation Conference10.1145/337292.337582(567-572)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337582
Lemieux GBrown SVranesic DKahng ASarrafzadeh M(1997)On two-step routing for FPGASProceedings of the 1997 international symposium on Physical design10.1145/267665.267682(60-66)Online publication date: 1-Apr-1997
https://dl.acm.org/doi/10.1145/267665.267682
Chih-Chang Lin Chang DYu-Liang Wu Marek-Sadowska M(1996)Time-multiplexed routing resources for FPGA designProceedings of Custom Integrated Circuits Conference10.1109/CICC.1996.510532(152-155)Online publication date: 1996
https://doi.org/10.1109/CICC.1996.510532
Brown SKhellah MVranesic Z(1996)Minimizing FPGA Interconnect DelaysIEEE Design & Test10.1109/54.54453213:4(16-23)Online publication date: 1-Dec-1996
https://dl.acm.org/doi/10.1109/54.544532
Yu-Liang Wu Marek-Sadowska M(1995)Routing on regular segmented 2-D FPGAsProceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair10.1109/ASPDAC.1995.486241(329-334)Online publication date: 1995
https://doi.org/10.1109/ASPDAC.1995.486241

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Rules of Designing Routing Metrics for Greedy, Face, and Combined Greedy-Face Routing

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Rules of Designing Routing Metrics for Greedy, Face, and Combined Greedy-Face Routing

Fault tolerant greedy perimeter stateless routing in wireless network

Greedy Routing by Network Distance Embedding

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