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Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Published: 03 June 2012 Publication History

Abstract

Continuous technology scaling has made aging mechanisms such as Negative Bias Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip (NoC) designs. In this paper, we model the effects of these aging mechanisms on NoC components such as routers and links using a novel reliability metric called Traffic Threshold per Epoch (TTpE). We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads caused due to aging degradation but also minimizes the stress experienced by heavily utilized routers and links. To solve this problem, we propose an aging-aware adaptive routing algorithm and a router microarchitecture that routes the packets along the paths which are both least congested and experience minimum aging stress. After an extensive experimental analysis using real workloads, we observe a 13%, 12.7% average overhead reduction in network latency and Energy-Delay-Product-Per-Flit (EDPPF) and a 10.4% improvement in performance using our aging-aware routing algorithm.

References

[1]
{SR1} Chang, J., and Sohi, G. S. Cooperative cache partitioning for chip multiprocessors. In International Conference on Supercomputing (2007).
[2]
{SR2} Gratz, P., Grot, B., and Keckler, S. W. Regional congestion awareness for load balance in networks-on-chip. In HPCA (2008).
[3]
{SR3} Chang, Y. C., Chiu, C. T, and Lin, S. Y. On the design and analysis of fault tolerant noc architecture using spare routers. In ASP-DAC (2011).
[4]
{SR4} Wang, L. T., Stroud, C. E, and Touba, N. A. System-on-Chip test architectures: Nanometer design for testability. Morgan Kaufmann (2008).
[5]
{SR5} Fu, X., Tao, L., and Fortes, J. A. Architecting reliable multi-core network-on-chip for small scale processing technology. In DSN (2010).
[6]
{SR6} Chan, T., Sartori, J., Gupta, P., and Kumar, R. On the efficacy of NBTI mitigation techniques. In DATE (2011).
[7]
{SR7} Bhardwaj, S., Wang, W., Vattikonda, R., Cao, Y., and Vrudhula, S. Predictive modeling of the NBTI effect for reliable design. In CICC (2006).
[8]
{SR8} Chang, H., and Sapatnekar, S. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In ICCAD (2003).
[9]
{SR9} Navidi, W. Statistics for engineers and scientists. McGraw Hill (2010).
[10]
{SR10} Sun, J., Kodi, A. K., Louri, A., and Wang, J. M. NBTI aware workload balancing in multi-core systems. In ISQED (2009).
[11]
{SR11} Datta, B., and Burleson, W. Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance. In GLSVLSI (2010).
[12]
{SR12} Sun, M., Pecht, M. G., and Barbe, D. Lifetime RC time delay of on-chip copper interconnect. In IEEE Tran. on Semiconductor Manufacturing (2002).

Cited By

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  • (2022)HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip ArchitectureIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.3147407(1-1)Online publication date: 2022
  • (2022)Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router MicroarchitectureMicroprocessors & Microsystems10.1016/j.micpro.2022.10452691:COnline publication date: 1-Jun-2022
  • (2021)Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network PerspectiveIEEE Access10.1109/ACCESS.2021.31231069(149399-149422)Online publication date: 2021
  • Show More Cited By

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cover image ACM Conferences
DAC '12: Proceedings of the 49th Annual Design Automation Conference
June 2012
1357 pages
ISBN:9781450311991
DOI:10.1145/2228360
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 June 2012

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Author Tags

  1. NBTI
  2. NoC
  3. aging
  4. electromigration
  5. routing algorithms

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DAC '12
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DAC '12: The 49th Annual Design Automation Conference 2012
June 3 - 7, 2012
California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2022)HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip ArchitectureIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.3147407(1-1)Online publication date: 2022
  • (2022)Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router MicroarchitectureMicroprocessors & Microsystems10.1016/j.micpro.2022.10452691:COnline publication date: 1-Jun-2022
  • (2021)Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network PerspectiveIEEE Access10.1109/ACCESS.2021.31231069(149399-149422)Online publication date: 2021
  • (2020)DRAIN: Deadlock Removal for Arbitrary Irregular Networks2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00044(447-460)Online publication date: Feb-2020
  • (2019)Intra and Inter Routing based Lifetime Improvement Method for VFI Network-on-ChipInternational Journal of Information and Electronics Engineering10.18178/IJIEE.2019.9.1.6979:1(12-18)Online publication date: Mar-2019
  • (2019)A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285514938:7(1373-1377)Online publication date: Jul-2019
  • (2019)An Aging-Aware Routing Algorithm for Improving Reliability in NoC-Based Multicore Systems2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00240(1749-1756)Online publication date: Aug-2019
  • (2018)Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2018.8645011(25-30)Online publication date: Oct-2018
  • (2018)AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.278017329:4(772-788)Online publication date: 1-Apr-2018
  • (2017)Online monitoring and adaptive routing for aging mitigation in NoCsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130395(67-72)Online publication date: 27-Mar-2017
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