research-article

Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits

Authors:

Chin-Cheng Kuo,

Yi-Kan ChengAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 1113 - 1118

https://doi.org/10.1145/2228360.2228563

Published: 03 June 2012 Publication History

Abstract

This paper proposes efficient trimmed-sample Monte Carlo (TSMC) methodology and novel yield-aware design flow for analog circuits. This approach focuses on "trimming simulation samples" to speedup MC analysis. The best possible yield and the worst performance are provided "before" MC simulations such that designers can stop MC analysis and start improving circuits earlier. Moreover, this work can combine with variance reduction techniques or low discrepancy sequences to reduce the MC simulation cost further. Using Latin Hypercube Sampling as an example, this approach gives 29x to 54x speedup over traditional MC analysis and the yield estimation errors are all smaller than 1%. For analog system designs, the proposed flow is still efficient for high-level MC analysis, as demonstrated by a PLL system.

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Cited By

Canelas AGuilherme JHorta NCanelas AGuilherme JHorta N(2020)Conclusion and Future WorkYield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies10.1007/978-3-030-41536-5_7(225-230)Online publication date: 21-Mar-2020
https://doi.org/10.1007/978-3-030-41536-5_7
Canelas AGuilherme JHorta NCanelas AGuilherme JHorta N(2020)Yield Estimation Techniques Related WorkYield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies10.1007/978-3-030-41536-5_3(65-95)Online publication date: 21-Mar-2020
https://doi.org/10.1007/978-3-030-41536-5_3
Mirzaie NByun G(2018)An Optimal Design Methodology for Yield-Improved and Low-Power Pipelined ADCIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2017.277357931:1(130-135)Online publication date: Feb-2018
https://doi.org/10.1109/TSM.2017.2773579
Show More Cited By

Index Terms

Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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DAC '12

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DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Canelas AGuilherme JHorta NCanelas AGuilherme JHorta N(2020)Conclusion and Future WorkYield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies10.1007/978-3-030-41536-5_7(225-230)Online publication date: 21-Mar-2020
https://doi.org/10.1007/978-3-030-41536-5_7
Canelas AGuilherme JHorta NCanelas AGuilherme JHorta N(2020)Yield Estimation Techniques Related WorkYield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies10.1007/978-3-030-41536-5_3(65-95)Online publication date: 21-Mar-2020
https://doi.org/10.1007/978-3-030-41536-5_3
Mirzaie NByun G(2018)An Optimal Design Methodology for Yield-Improved and Low-Power Pipelined ADCIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2017.277357931:1(130-135)Online publication date: Feb-2018
https://doi.org/10.1109/TSM.2017.2773579
Zeng WZhu HZeng XZhou DLiu RLi X(2017)C-YESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261392736:6(899-912)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2613927
Mirzaie NShamsi HByun G(2017)Resilient design of current steering DACs using a transistor level approachAnalog Integrated Circuits and Signal Processing10.1007/s10470-016-0859-190:1(29-41)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1007/s10470-016-0859-1
Lee HHan CLi J(2016)A Multicircuit Simulator Based on Inverse Jacobian Matrix ReuseIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.250130835:7(1130-1137)Online publication date: 1-Jul-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2501308
Mirzaie NShamsi HByun G(2016)Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithmInternational Journal of Circuit Theory and Applications10.1002/cta.227945:6(744-763)Online publication date: 30-Nov-2016
https://doi.org/10.1002/cta.2279
Seghaier IZaki MTahar SJones ALi HCoskun AMargala M(2015)Statistically Validating the Impact of Process Variations on Analog and Mixed Signal DesignsProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742122(99-102)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742122

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