Abstract
Scaling of conventional interconnects faces two major challenges: increased effective copper resistivity at nano-scale linewidth, and degraded copper wire reliability at higher current density. Analysis shows that when the linewidth of Cu wire scales from 30 nm to 10 nm, the resistance per unit length increases by more than 10 times (wire aspect ratio =1) due to increased surface scattering and grain boundary scattering. Such significant wire resistance increase brings significant problems such as increased chip power consumption, and degradation of wire lifetime due to increased Joule heating. At smaller linewidth, wires also have to withstand a higher current density to deliver the same current. The higher current density shortens the wire electromigration lifetime and causes reliability concerns.
Degraded wire conductivity and current carrying capability could potentially be a big problem for deeply scaled devices. The problems manifest themselves first in memory arrays where the wire linewidth must be kept narrow for high device density and the wire length must be kept long for high array efficiency. We studied the impact of Cu interconnect scaling on the write/read margin, energy dissipation, speed, and reliability of resistive cross-point memory array. Results show that performance degradations are strongly dependent on the memory device parameters and memory array sizes: ron (memory on resistance) below 100KΩ and array size > 1Mb lead to write margin < 55%, read margin < 5%, and wire energy > 1pJ for wire size smaller than 20 nm. Also, in order to keep the maximum current density below the electromigration threshold of Cu, the programming current has to be engineered below 0.1μA for wire size <10 nm. In addition, further decrease in programming current is required for larger-scale arrays. Such low programming current, associated with an even lower read current, will lead to write/read speeds too slow to be practical.
In recent years, carbon-based nanomaterials such as carbon nanotubes (CNT) and graphene have been explored as potential candidates for future interconnect materials. It has been demonstrated that CNT and graphene wires can be successfully integrated with CMOS and operate at GHz frequency range. Besides the potential performance benefit CNT/graphene can offer because of its superior conductivity at nano-scale, it is also important to understand the reliability improvement carbon wires can offer. We studied both breakdown current density and lifetime of graphene interconnects. Results show that CVD graphene can withstand current density up to 108 MA/cm2. However when exposed to air, graphene wire lifetime is limited by oxidation. Therefore optimizing the capping material for graphene interconnect will substantially improve the wire lifetime.
Interconnect has always been an important part of the integrated circuit (IC). With the progressive miniaturization of semiconductor devices, interconnect wires is becoming one of the key components that decide IC performance: the parasitic capacitance associated with interconnects accounts for about 50% of the chip power consumption; current drivability of copper also limits the performance of deeply scaled devices in the sub-10nm node. In this paper, we give an overview of the scaling challenges that modern interconnect technology is facing, and its implications for the performance of sub-10nm memory arrays. We will then discuss how carbon-based nanomaterials can help address the scaling challenges of interconnect technology and review recent research progress on carbon-based interconnects.
