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Word level model checking—avoiding the Pentium FDIV error

Authors:

E. M. Clarke,

M. Khaira,

X. ZhaoAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 645 - 648

https://doi.org/10.1145/240518.240640

Published: 01 June 1996 Publication History

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References

[1]

R. E. Bryant and Y. A. Chen. Verification of arithmetic functions with Binary Moment Diagrams. In Proceedings of the 31tnd A CM/IEEE Design Automation Con- }erence, pages 535-541. IEEE Computer Society Press, June 1995.

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J. R. Butch, E. M. Clarke, K. L. McMillan, D. L. Dill, and L. J. Hwang. Symbolic model check, g: 102o states and beyond. Information and Computation, 98(2):142- 170, June 1992.

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E. M. Clarke and X. Zhao. Analytica: A theorem prover for Mathematica. The Journal of Mathematica, 3(1), 1993.

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Cited By

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Konrad AScholl CMahzoon AGroße DDrechsler R(2024)Divider verification using symbolic computer algebra and delayed don’t care optimization: theory and practical implementationFormal Methods in System Design10.1007/s10703-024-00452-3Online publication date: 24-May-2024
https://doi.org/10.1007/s10703-024-00452-3
Bjesse P(2008)Word-level sequential memory abstraction for model checkingProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517440(1-9)Online publication date: 17-Nov-2008
https://dl.acm.org/doi/10.5555/1517424.1517440
Chen LZhang YXu C(2006)Fully Utilized and Low Memory-bandwidth Architecture Design of Variable Block-size Motion Estimation for H.264/AVCTENCON 2006 - 2006 IEEE Region 10 Conference10.1109/TENCON.2006.344196(1-4)Online publication date: Nov-2006
https://doi.org/10.1109/TENCON.2006.344196
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Index Terms

Word level model checking—avoiding the Pentium FDIV error
1. Hardware
  1. Hardware validation
    1. Functional verification

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Model checking (Baier and Katoen in Principles of model checking, MIT Press, Cambridge, 2008; Clarke et al. in Model checking, MIT Press, Cambridge, 2001) is an automatic technique to formally verify that a given specification of a concurrent system ...

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DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Konrad AScholl CMahzoon AGroße DDrechsler R(2024)Divider verification using symbolic computer algebra and delayed don’t care optimization: theory and practical implementationFormal Methods in System Design10.1007/s10703-024-00452-3Online publication date: 24-May-2024
https://doi.org/10.1007/s10703-024-00452-3
Bjesse P(2008)Word-level sequential memory abstraction for model checkingProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517440(1-9)Online publication date: 17-Nov-2008
https://dl.acm.org/doi/10.5555/1517424.1517440
Chen LZhang YXu C(2006)Fully Utilized and Low Memory-bandwidth Architecture Design of Variable Block-size Motion Estimation for H.264/AVCTENCON 2006 - 2006 IEEE Region 10 Conference10.1109/TENCON.2006.344196(1-4)Online publication date: Nov-2006
https://doi.org/10.1109/TENCON.2006.344196
Chen YHuang Z(2006)A SAT-Based Arithmetic Circuit Bug-Hunting MethodTENCON 2006 - 2006 IEEE Region 10 Conference10.1109/TENCON.2006.344044(1-4)Online publication date: Nov-2006
https://doi.org/10.1109/TENCON.2006.344044
Chen YBryant R(2006)An efficient graph representation for arithmetic circuit verificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.96943720:12(1443-1454)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.969437
Chen YBryant R(2005)Verification of floating-point addersComputer Aided Verification10.1007/BFb0028769(488-499)Online publication date: 18-Jun-2005
https://doi.org/10.1007/BFb0028769
Rushby J(2005)Mechanized formal methods: Progress and prospectsFoundations of Software Technology and Theoretical Computer Science10.1007/3-540-62034-6_36(43-51)Online publication date: 3-Jun-2005
https://doi.org/10.1007/3-540-62034-6_36
Clarke EMcMillan KCampos SHartonas-Garmhausen V(2005)Symbolic model checkingComputer Aided Verification10.1007/3-540-61474-5_93(419-422)Online publication date: 3-Jun-2005
https://doi.org/10.1007/3-540-61474-5_93
Clarke EGerman SZhao X(2005)Verifying the SRT division algorithm using theorem proving techniquesComputer Aided Verification10.1007/3-540-61474-5_62(111-122)Online publication date: 3-Jun-2005
https://doi.org/10.1007/3-540-61474-5_62
Déharbe D(2003)A tutorial introduction to symbolic model checkingLogic for concurrency and synchronisation10.5555/948165.948172(215-237)Online publication date: 1-Jan-2003
https://dl.acm.org/doi/10.5555/948165.948172
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The Unabridged Pentium 4: IA32 Processor Genealogy

Pentium Processor System Architecture

Model checking: recent improvements and applications

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The Unabridged Pentium 4: IA32 Processor Genealogy

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Model checking: recent improvements and applications

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