research-article

Simultaneous analog placement and routing with current flow and current density considerations

Authors:

Hsing-Chih Chang Chien,

Yao-Wen ChangAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 5, Pages 1 - 6

https://doi.org/10.1145/2463209.2488739

Published: 29 May 2013 Publication History

Abstract

Current-flow and current-density are two major considerations for placement and routing of analog layout synthesis. The current-flow constraints are specified to the critical nets with monotonic current/signal paths to reduce parasitic impacts. The current-density constraints are usually specified on the nets with variable wire widths to avoid the IR-drop and electromigration problems. In this paper, we propose the first work to simultaneously consider current-flow and current-density constraints while placing and routing the analog circuits with minimized chip area, routed wirelength, bend numbers, via counts, and coupling noise at the same time. We first present an enhanced B*-tree representation to simultaneously model modules and interconnects for an analog circuit. Then a simultaneous placement and routing algorithm is presented to generate a layout while satisfying the current-flow and current-density constraints with minimized chip area, routed wire-length, bend numbers, via counts, and coupling noise. Experimental results show that our approach can obtain better layout results and satisfy all specified constraints while optimizing circuit performance.

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Cited By

Xu PLi JHo TYu BZhu K(2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473859
Zhu KChen HLiu MPan D(2023)Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323036742:8(2689-2702)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3230367
Dhar TS RPoojary JYaldiz SBurns SHarjani RSapatnekar S(2022)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774621(148-153)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774621
Show More Cited By

Index Terms

Simultaneous analog placement and routing with current flow and current density considerations
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Xu PLi JHo TYu BZhu K(2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473859
Zhu KChen HLiu MPan D(2023)Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323036742:8(2689-2702)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3230367
Dhar TS RPoojary JYaldiz SBurns SHarjani RSapatnekar S(2022)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774621(148-153)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774621
Lin YLi YFang DMadhusudan MSapatnekar SHarjani RHu J(2022)Are Analytical Techniques Worthwhile for Analog IC Placement?2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774498(154-159)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774498
Gusmão APóvoa RHorta NLourenço NMartins R(2022)DeepPlacerApplied Soft Computing10.1016/j.asoc.2021.108188115:COnline publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1016/j.asoc.2021.108188
Burns SChen HDhar THarjani RHu JKarmokar NKunal KLi YLin YLiu MMadhusudan MMukherjee PPan DPoojary JRamprasath SSapatnekar SSharma AXu WYaldiz SZhu K(2022)Machine Learning for Analog LayoutMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_17(505-544)Online publication date: 10-Aug-2022
https://doi.org/10.1007/978-3-031-13074-8_17
Budak APan DChen HZhu KLiu MAlawieh MZhang SShi WTang X(2022)CAD for Analog/Mixed‐Signal Integrated CircuitsAdvances in Semiconductor Technologies10.1002/9781119869610.ch3(43-60)Online publication date: 30-Sep-2022
https://doi.org/10.1002/9781119869610.ch3
Dhar TKunal KLi YMadhusudan MPoojary JSharma AXu WBurns SHarjani RHu JKirkpatrick DMukherjee PYaldiz SSapatnekar S(2021)ALIGN: A System for Automating Analog LayoutIEEE Design & Test10.1109/MDAT.2020.304217738:2(8-18)Online publication date: Apr-2021
https://doi.org/10.1109/MDAT.2020.3042177
Martins RLourenço NPóvoa RHorta N(2021)Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealingEngineering Applications of Artificial Intelligence10.1016/j.engappai.2020.10410298(104102)Online publication date: Feb-2021
https://doi.org/10.1016/j.engappai.2020.104102
Zhu KChen HLiu MTang XSun NPan DXie Y(2020)Effective analog/mixed-signal circuit placement considering system signal flowProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415625(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415625
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