research-article

Performance evaluation of Intel® transactional synchronization extensions for high-performance computing

Authors:

Richard M. Yoo,

Christopher J. Hughes,

Ravi RajwarAuthors Info & Claims

SC '13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

Article No.: 19, Pages 1 - 11

https://doi.org/10.1145/2503210.2503232

Published: 17 November 2013 Publication History

Abstract

Intel has recently introduced Intel^® Transactional Synchronization Extensions (Intel^® TSX) in the Intel 4th Generation Core™ Processors. With Intel TSX, a processor can dynamically determine whether threads need to serialize through lock-protected critical sections. In this paper, we evaluate the first hardware implementation of Intel TSX using a set of high-performance computing (HPC) workloads, and demonstrate that applying Intel TSX to these workloads can provide significant performance improvements. On a set of real-world HPC workloads, applying Intel TSX provides an average speedup of 1.41x. When applied to a parallel user-level TCP/IP stack, Intel TSX provides 1.31x average bandwidth improvement on network intensive applications. We also demonstrate the ease with which we were able to apply Intel TSX to the various workloads.

References

[1]

D. A. Bader and K. Madduri. Design and implementation of the HPCS graph analysis benchmark on symmetric multiprocessors. In Proceedings of the 12th International Conference on High Performance Computing, pages 465--476, 2005.

Digital Library

[2]

C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pages 72--81, 2008.

Digital Library

[3]

J. Chhugani, C. Kim, H. Shukla, J. Park, P. Dubey, J. Shalf, and H. D. Simon. Billion-particle SIMD-friendly two-point correlation on large-scale HPC cluster systems. In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, pages 1:1--1:11, 2012.

Digital Library

[4]

C. Click. Azul's experience with hardware transactional memory. In HP Labs Bay Area Transactional Memory Workshop, 2009.

[5]

D. Dice, Y. Lev, V. J. Marathe, M. Moir, D. Nussbaum, and M. Olszewski. Simplifying concurrent algorithms by exploiting hardware transactional memory. In Proceedings of the 22nd ACM Symposium on Parallelism in Algorithms and Architectures, pages 325--334, 2010.

Digital Library

[6]

D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 157--168, 2009.

Digital Library

[7]

D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In Proceedings of the 2006 International Conference on Distributed Computing, pages 194--208.

Digital Library

[8]

P. Dudnik and M. M. Swift. Condition variables and transactional memory: Problem or opportunity? In the 4th ACM SIGPLAN Workshop on Transactional Computing, 2009.

[9]

H. Feng, R. F. V. der Wijngaart, R. Biswas, and C. Mavriplis. Unstructured Adaptive (UA) NAS parallel benchmark, version 1.0. Technical report, NASA Technical Report NAS-04-006, 2004.

[10]

V. Gajinov, F. Zyulkyarov, O. S. Unsal, A. Cristal, E. Ayguade, T. Harris, and M. Valero. QuakeTM: Parallelizing a complex sequential application using transactional memory. In Proceedings of the 23rd International Conference on Supercomputing, pages 126--135, 2009.

Digital Library

[11]

M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 1993 Annual International Symposium on Computer Architecture, pages 289--300.

Digital Library

[12]

Intel Corporation. Intel architecture instruction set extensions programming reference. Chapter 8: Intel transactional synchronization extensions. 2012.

[13]

Intel Corporation. Intel 64 and IA-32 architectures optimization reference manual. Chapter 12: Intel TSX recommendations. 2013.

[14]

C. Jacobi, T. Slegel, and D. Greiner. Transactional memory architecture and implementation for IBM System z. In Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, pages 25--36, 2012.

Digital Library

[15]

D. Kalamkar, J. Trzasko, S. Sridharan, M. Smelyanskiy, D. Kim, A. Manduca, Y. Shu, M. Bernstein, B. Kaul, and P. Dubey. High performance non-uniform FFT on modern x86-based multi-core systems. In Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, pages 449--460, 2012.

Digital Library

[16]

G. Kestor, V. Karakostas, O. S. Unsal, A. Cristal, I. Hur, and M. Valero. RMS-TM: A comprehensive benchmark suite for transactional memory systems. In Proceedings of the 2nd Joint WOSP/SIPEW International Conference on Performance Engineering, pages 335--346, 2011.

Digital Library

[17]

C. Kim, J. Park, N. Satish, H. Lee, P. Dubey, and J. Chhugani. CloudRAMSort: Fast and efficient large-scale distributed RAM sort on shared-nothing cluster. In Proceedings of the 2012 ACM SIGMOD International Conference on Management of Data, pages 841--850.

Digital Library

[18]

B. W. Lampson and D. D. Redell. Experience with processes and monitors in Mesa. Commun. ACM, 23(2):105--117, 1980.

Digital Library

[19]

C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In Proceedings of the 2008 IEEE International Symposium on Workload Characterization, pages 35--46.

[20]

M. Mitran and V. Vokhshoori. Evaluating the zEC12 transactional execution facility. IBM Systems Magazine, 2012.

[21]

OpenMP Architecture Review Board. OpenMP Application Program Interface Version 3.1, 2011.

[22]

R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th Annual IEEE/ACM International Symposium on Microarchitecture, pages 294--305, 2001.

Digital Library

[23]

M. Schindewolf, B. Bihari, J. Gyllenhaal, M. Schulz, A. Wang, and W. Karl. What scientific applications can benefit from hardware transactional memory? In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, pages 90:1--90:11, 2012.

Digital Library

[24]

L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan. Larrabee: A many-core x86 architecture for visual computing. In ACM SIGGRAPH 2008 papers, pages 18:1--18:15.

Digital Library

[25]

A. Skyrme and N. Rodriguez. From locks to transactional memory: Lessons learned from porting a real-world application. In the 8th ACM SIGPLAN Workshop on Transactional Computing, 2013.

[26]

J. M. Stone, H. S. Stone, P. Heidelberger, and J. Turek. Multiple reservations and the Oklahoma update. Parallel Distributed Technology: Systems Applications, IEEE, 1(4):58--71, 1993.

Digital Library

[27]

Transactional Memory Specification Drafting Group. Draft specification of transactional language constructs for C++, version: 1.1. 2012.

[28]

T. Vyas, Y. Liu, and M. Spear. Transactionalizing legacy code: An experience report using GCC and memcached. In the 8th ACM SIGPLAN Workshop on Transactional Computing, 2013.

[29]

A. Wang, M. Gaudet, P. Wu, J. N. Amaral, M. Ohmacht, C. Barton, R. Silvera, and M. Michael. Evaluation of Blue Gene/Q hardware support for transactional memories. In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, pages 127--136, 2012.

Digital Library

[30]

R. M. Yoo, Y. Ni, A. Welc, B. Saha, A.-R. Adl-Tabatabai, and H.-H. S. Lee. Kicking the tires of software transactional memory: Why the going gets tough. In Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures, pages 265--274, 2008.

Digital Library

Cited By

Khalaji MBrown TDaudjee KAksenov VLee IChabbi MSteuwer M(2024)Practical Hardware Transactional vEB TreesProceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming10.1145/3627535.3638504(215-228)Online publication date: 2-Mar-2024
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Performance evaluation of Intel® transactional synchronization extensions for high-performance computing

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cover image ACM Conferences

SC '13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

November 2013

1123 pages

ISBN:9781450323789

DOI:10.1145/2503210

General Chair:
William Gropp
University of Illinois at Urbana-Champaign, Urbana, Illinois
,
Program Chair:
Satoshi Matsuoka
Tokyo Institute of Technology, Tokyo, Japan

Copyright © 2013 ACM.

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Published: 17 November 2013

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SC13: International Conference for High Performance Computing, Networking, Storage and Analysis

November 17 - 21, 2013

Colorado, Denver

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SC '13 Paper Acceptance Rate 91 of 449 submissions, 20%;

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https://dl.acm.org/doi/10.1145/3627535.3638504
Kim HHahn CKim HShin YHur J(2024)Deep Learning-Based Detection for Multiple Cache Side-Channel AttacksIEEE Transactions on Information Forensics and Security10.1109/TIFS.2023.334008819(1672-1686)Online publication date: 2024
https://doi.org/10.1109/TIFS.2023.3340088
Nicolás-Conesa VTitos-Gil RFernández-Pascual RAcacio MRos A(2024)Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00067(840-855)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00067
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Salamanca JBaldassin A(2024)Using Hardware-Transactional-Memory Support to Implement Speculative Task ExecutionJournal of Parallel and Distributed Computing10.1016/j.jpdc.2024.104939(104939)Online publication date: Jul-2024
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Li YLiu HGao JZhang JGuan ZChen Z(2024)Accelerating block lifecycle on blockchain via hardware transactional memoryJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104779184(104779)Online publication date: Mar-2024
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