research-article

RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits

Authors:

Niraj K. JhaAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 10, Issue 2

Article No.: 14, Pages 1 - 25

https://doi.org/10.1145/2564923

Published: 06 March 2014 Publication History

Abstract

In this article, we propose a flexible and efficient reversible logic synthesizer. It exploits the complementary advantages of two methods: Reed-Muller Reversible Logic Synthesis (RMRLS) and Decision Diagram Synthesis (DDS), and is thus called Reed-Muller Decision Diagram Synthesis (RMDDS). RMRLS does not scale to a large number of qubits (i.e., quantum bits). DDS tools, even though efficient, add a large number of ancillary qubits and typically incur much higher quantum cost than necessary. RMDDS overcomes these obstacles. It is flexible in the sense that users can either optimize the number of qubits or the quantum cost in the circuit implementation. It is also efficient because the circuits can be synthesized within user-defined CPU times. This combination of flexibility and efficiency has been missing from synthesizers presented earlier. When used to synthesize reversible functions, RMDDS reduces the number of qubits by up to 79.2% (average of 54.6%) when the synthesis objective is to minimize the number of qubits and the quantum cost by up to 71.5% (average of 35.7%) when the synthesis objective is to minimize quantum cost, relative to DDS methods. For irreversible functions (which are automatically embedded in reversible functions), the corresponding best (average) reductions in the number of qubits is 42.1% (22.5%) when minimizing the number of qubits, and in quantum cost, it is 63.0% (25.9%) when minimizing quantum cost.

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Cited By

He JXu HFeng SDu M(2022)Heuristic Reordering Strategy for Quantum Circuit Mapping on LNN ArchitecturesComputational Intelligence and Neuroscience10.1155/2022/17659552022Online publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1155/2022/1765955
Bu DDeng JTang PYang S(2022)Reversible Circuit Synthesis Method Using Sub-graphs of Shared Functional Decision DiagramsThe Computer Journal10.1093/comjnl/bxac10766:10(2574-2592)Online publication date: 1-Aug-2022
https://doi.org/10.1093/comjnl/bxac107
Bu DYan JTang PYuan H(2022)Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision DiagramsJournal of Electronic Testing10.1007/s10836-022-05987-z38:1(39-62)Online publication date: 25-Mar-2022
https://doi.org/10.1007/s10836-022-05987-z
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Index Terms

RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 10, Issue 2

February 2014

143 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2590828

Issue’s Table of Contents

Copyright © 2014 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 06 March 2014

Accepted: 01 September 2012

Revised: 01 September 2012

Received: 01 May 2012

Published in JETC Volume 10, Issue 2

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Cited By

He JXu HFeng SDu M(2022)Heuristic Reordering Strategy for Quantum Circuit Mapping on LNN ArchitecturesComputational Intelligence and Neuroscience10.1155/2022/17659552022Online publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1155/2022/1765955
Bu DDeng JTang PYang S(2022)Reversible Circuit Synthesis Method Using Sub-graphs of Shared Functional Decision DiagramsThe Computer Journal10.1093/comjnl/bxac10766:10(2574-2592)Online publication date: 1-Aug-2022
https://doi.org/10.1093/comjnl/bxac107
Bu DYan JTang PYuan H(2022)Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision DiagramsJournal of Electronic Testing10.1007/s10836-022-05987-z38:1(39-62)Online publication date: 25-Mar-2022
https://doi.org/10.1007/s10836-022-05987-z
Stojković SStanković RMoraga CStanković M(2019)Reversible Circuits Synthesis from Functional Decision Diagrams by using Node Dependency MatricesJournal of Circuits, Systems and Computers10.1142/S0218126620500796(2050079)Online publication date: 10-Jun-2019
https://doi.org/10.1142/S0218126620500796
Bu DWang P(2019)An improved KFDD based reversible circuit synthesis methodIntegration10.1016/j.vlsi.2019.04.008Online publication date: May-2019
https://doi.org/10.1016/j.vlsi.2019.04.008
Alwardi ZWille RDrechsler R(2018)Synthesis of Reversible Circuits Using Conventional Hardware Description Languages2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)10.1109/ISMVL.2018.00025(97-102)Online publication date: May-2018
https://doi.org/10.1109/ISMVL.2018.00025
Jegier JKemtopf P(2017)Application of the maximum weighted matching to quantum cost reduction in reversible circuits2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems10.23919/MIXDES.2017.8005188(224-228)Online publication date: Jun-2017
https://doi.org/10.23919/MIXDES.2017.8005188
Alwardi ZWille RDrechsler R(2017)Extensions to the Reversible Hardware Description Language SyReC2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)10.1109/ISMVL.2017.41(185-190)Online publication date: May-2017
https://doi.org/10.1109/ISMVL.2017.41
Amy MRoetteler MSvore K(2017)Verified Compilation of Space-Efficient Reversible CircuitsComputer Aided Verification10.1007/978-3-319-63390-9_1(3-21)Online publication date: 13-Jul-2017
https://doi.org/10.1007/978-3-319-63390-9_1
Parent ARoetteler MSvore K(2017)REVS: A Tool for Space-Optimized Reversible Circuit SynthesisReversible Computation10.1007/978-3-319-59936-6_7(90-101)Online publication date: 25-May-2017
https://doi.org/10.1007/978-3-319-59936-6_7
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