research-article

MIC-Check: a distributed check pointing framework for the intel many integrated cores architecture

Authors:

Raghunath Rajachandrasekar,

Dhabaleswar K. (DK) PandaAuthors Info & Claims

HPDC '14: Proceedings of the 23rd international symposium on High-performance parallel and distributed computing

Pages 121 - 124

https://doi.org/10.1145/2600212.2600713

Published: 23 June 2014 Publication History

Get Access

Abstract

The advent of many-core architectures like Intel MIC is enabling the design of increasingly capable supercomputers within reasonable power budgets. Fault-tolerance is becoming more important with the increased number of components and the complexity in these heterogeneous clusters. Checkpoint-restart mechanisms have been traditionally used to enhance the dependability of applications, and to enable dynamic task rescheduling in the face of system failures. Naive checkpointing protocols, which are predominantly I/O-intensive, face severe performance bottlenecks on the Xeon Phi architecture due to several inherent and acquired limitations. Consequently, existing checkpointing frameworks are not capable of serving distributed MPI applications that leverage heterogeneous hardware architectures. This paper discusses the I/O limitations on the Xeon Phi system, and describes the architecture and design of a novel distributed checkpointing framework, namely MIC-Check, for HPC applications running on it.

References

[1]

Improving File IO performance on Intel Xeon Phi. http://software.intel.com/en-us/blogs/2014/01/07/improving-file-io-performance-on-intel-xeon-phi.

Google Scholar

[2]

Intel MIC Architecture. http://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html.

Google Scholar

[3]

XEON-PHI Software Developer's Guide. http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-phi-software-developers-guide.pdf.

Google Scholar

[4]

Top500 Supercomputer List. http://www.top500.org/lists/2013/11, November 2013.

Google Scholar

[5]

K. S. et al. Early Experiences Porting Scientific Applications to the Many Integrated Core (MIC) Platform. In TACC-Intel Tech. Rep, 2012.

Google Scholar

[6]

S. P. et al. MVAPICH-PRISM: A Proxy-based Communication Framework using InfiniBand and SCIF for Intel MIC clusters. In SC'13, 2013.

Google Scholar

[7]

TACC. Stampede Supercomputer. http://www.top500.org/system/177931.

Google Scholar

Cited By

View all

Elnawawy HTuck JByrd G(2023)PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00015(74-85)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00015
Alshboul MRamrakhyani PWang WTuck JSolihin Y(2021)BBB: Simplifying Persistent Programming using Battery-Backed Buffers2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00019(111-124)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00019
Parasyris KKeller KBautista-Gomez LUnsal O(2020)Checkpoint Restart Support for Heterogeneous HPC Applications2020 20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGRID)10.1109/CCGrid49817.2020.00-69(242-251)Online publication date: May-2020
https://doi.org/10.1109/CCGrid49817.2020.00-69
Show More Cited By

Index Terms

MIC-Check: a distributed check pointing framework for the intel many integrated cores architecture
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
2. Software and its engineering
  1. Software organization and properties
    1. Extra-functional properties
      1. Software fault tolerance
        Checkpoint / restart

Recommendations

Efficient intra-node communication on Intel-MIC clusters
CCGRID '13: Proceedings of the 13th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing

Accelerators and coprocessors have become a key component in modern supercomputing systems due to the superior performance per watt that they offer. Intel's Xeon Phi coprocessor packs up to 1 TFLOP of double precision performance in a single chip while ...
SPECTR: Scalable Parallel Short Read Error Correction on Multi-core and Many-core Architectures
ICPP '18: Proceedings of the 47th International Conference on Parallel Processing

Modern high throughput sequencing platforms can produce large amounts of short read DNA data at low cost. Error correction is an important but time-consuming initial step when processing this data in order to improve the quality of downstream analyses. ...
Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle-in-cell code

We present initial comparison performance results for Intel many integrated core MIC, Sandy Bridge SB, and graphical processing unit GPU. A 1D explicit electrostatic particle-in-cell code is used to simulate a two-stream instability in plasma. We ...

Comments

Information & Contributors

Information

Published In

HPDC '14: Proceedings of the 23rd international symposium on High-performance parallel and distributed computing

June 2014

334 pages

ISBN:9781450327497

DOI:10.1145/2600212

General Chairs:
Beth Plale
Indiana University, USA
,
Matei Ripeanu
University of British Columbia, CA
,
Program Chairs:
Franck Cappello
Argonne National Lab and INRIA, USA
,
Dongyan Xu
Purdue University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 June 2014

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

HPDC'14

Sponsor:

SIGARCH

HPDC'14: The 23rd International Symposium on High-Performance Parallel and Distributed Computing

June 23 - 27, 2014

BC, Vancouver, Canada

Acceptance Rates

HPDC '14 Paper Acceptance Rate 21 of 130 submissions, 16%;

Overall Acceptance Rate 166 of 966 submissions, 17%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
244
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Elnawawy HTuck JByrd G(2023)PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00015(74-85)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00015
Alshboul MRamrakhyani PWang WTuck JSolihin Y(2021)BBB: Simplifying Persistent Programming using Battery-Backed Buffers2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00019(111-124)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00019
Parasyris KKeller KBautista-Gomez LUnsal O(2020)Checkpoint Restart Support for Heterogeneous HPC Applications2020 20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGRID)10.1109/CCGrid49817.2020.00-69(242-251)Online publication date: May-2020
https://doi.org/10.1109/CCGrid49817.2020.00-69
Alshboul MElnawawy HElkhouly RKimura KTuck JSolihin Y(2019)Efficient Checkpointing with Recompute Scheme for Non-volatile Main MemoryACM Transactions on Architecture and Code Optimization10.1145/332309116:2(1-27)Online publication date: 29-May-2019
https://dl.acm.org/doi/10.1145/3323091
Wang TSambasivam STuck J(2018)Hardware supported permission checks on persistent objects for performance and programmabilityProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00046(466-478)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00046
Shin STuck JSolihin Y(2017)Hiding the Long Latency of Persist Barriers Using Speculative ExecutionACM SIGARCH Computer Architecture News10.1145/3140659.308024045:2(175-186)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080240
Shin STirukkovalluri STuck JSolihin YHunter HMoreno JEmer JSanchez D(2017)ProteusProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3124539(178-190)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3124539
Wang TSambasivam SSolihin YTuck JHunter HMoreno JEmer JSanchez D(2017)Hardware supported persistent object address translationProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123981(800-812)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123981
Shin STuck JSolihin Y(2017)Hiding the Long Latency of Persist Barriers Using Speculative ExecutionProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080240(175-186)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080240
Chen CDu YZuo KFang JYang C(2017)Toward fault-tolerant hybrid programming over large-scale heterogeneous clusters via checkpointing/restart optimizationThe Journal of Supercomputing10.1007/s11227-017-2116-5Online publication date: 20-Aug-2017
https://doi.org/10.1007/s11227-017-2116-5
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Efficient intra-node communication on Intel-MIC clusters

SPECTR: Scalable Parallel Short Read Error Correction on Multi-core and Many-core Architectures

Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle-in-cell code