research-article

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Authors:

Baris TaskinAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 283 - 288

https://doi.org/10.1145/2742060.2742092

Published: 20 May 2015 Publication History

Abstract

Clock skew scheduling is a common and well known technique to improve the performance of sequential circuits by exploiting the mismatches in the data path delays. Existing clock skew scheduling techniques, however, cannot effectively consider heavily gated clock networks where a local clock tree exists between clock gating cells and registers. A methodology is proposed in this paper to efficiently achieve clock skew scheduling in circuits with gated clock networks. The methodology is implemented via both linear programming and constraint graph based approaches, and evaluated using the largest ISCAS'89 benchmark circuits with clock gating. The results demonstrate up to approximately 21% reduction in clock period while maintaining the power savings achieved by clock gating. A conventional design flow is used for the experiments, demonstrating the applicability of the proposed algorithms to automation.

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Cited By

Tziouvaras ADimitriou GDossis MStamoulis G(2021)Frequency Scaling for High Performance of Low-End Pipelined ProcessorsAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0602886:2(763-775)Online publication date: Mar-2021
https://doi.org/10.25046/aj060288
Sitik CLiu WTaskin BSalman EHomayoun HTaskin BMohsenin TZhao W(2019)Low Voltage Clock Tree Synthesis with Local Gate ClustersProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318004(99-104)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318004
Noor TSalman E(2019)A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702507(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702507
Show More Cited By

Index Terms

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks
1. Hardware
  1. Very large scale integration design

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cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

Publication History

Published: 20 May 2015

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Semiconductor Research Corporation

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GLSVLSI '15

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SIGDA

GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

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GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Tziouvaras ADimitriou GDossis MStamoulis G(2021)Frequency Scaling for High Performance of Low-End Pipelined ProcessorsAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0602886:2(763-775)Online publication date: Mar-2021
https://doi.org/10.25046/aj060288
Sitik CLiu WTaskin BSalman EHomayoun HTaskin BMohsenin TZhao W(2019)Low Voltage Clock Tree Synthesis with Local Gate ClustersProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318004(99-104)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318004
Noor TSalman E(2019)A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702507(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702507
Liu WSalman ESitik CTaskin B(2016)Exploiting useful skew in gated low voltage clock trees2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7539124(2595-2598)Online publication date: May-2016
https://doi.org/10.1109/ISCAS.2016.7539124

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