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Global wires: harmful?

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Ralph H. J. M. OttenAuthors Info & Claims

ISPD '98: Proceedings of the 1998 international symposium on Physical design

April 1998

Pages 104 - 109

https://doi.org/10.1145/274535.274550

Published: 01 April 1998 Publication History

Abstract

In this paper a shift is proposed in the design of vlsi circuits. In conventional design higher levels of synthesis have to deliver a gate and net list, from which layout synthesis has to built a mask specification for manufacturing. Analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-off. These violations are used to hand an updated specification to synthesis. Such iteration is not desirable, and for really high performance not feasible. To come to a design flow, higher level synthesis should distribute delay over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.

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Cited By

Wu HHuang ZLi XZhu W(2024)AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RLIntegration10.1016/j.vlsi.2024.10221198(102211)Online publication date: Sep-2024
https://doi.org/10.1016/j.vlsi.2024.102211
Jung JNam GChung WShin Y(2019)Integrated Latch Placement and Cloning for Timing OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/330161324:2(1-17)Online publication date: 9-Feb-2019
https://dl.acm.org/doi/10.1145/3301613
Brenner UHermann AHoppmann NOchsendorf PDavoodi AYoung E(2015)BonnPlaceProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717778(9-16)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2717778
Show More Cited By

Index Terms

Global wires: harmful?
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design

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cover image ACM Conferences

ISPD '98: Proceedings of the 1998 international symposium on Physical design

April 1998

220 pages

ISBN:158113021X

DOI:10.1145/274535

Chairman:
M. Sarrafzadeh
Northwestern Univ., Evanston, IL

Copyright © 1998 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
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Association for Computing Machinery

New York, NY, United States

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Published: 01 April 1998

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ISPD98: International Symposium on Physical Design

April 6 - 8, 1998

California, Monterey, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Citations

Cited By

Wu HHuang ZLi XZhu W(2024)AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RLIntegration10.1016/j.vlsi.2024.10221198(102211)Online publication date: Sep-2024
https://doi.org/10.1016/j.vlsi.2024.102211
Jung JNam GChung WShin Y(2019)Integrated Latch Placement and Cloning for Timing OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/330161324:2(1-17)Online publication date: 9-Feb-2019
https://dl.acm.org/doi/10.1145/3301613
Brenner UHermann AHoppmann NOchsendorf PDavoodi AYoung E(2015)BonnPlaceProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717778(9-16)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2717778
Papa DMarkov IA. Papa DL. Markov I(2012)Physically-Driven Logic RestructuringMulti-Objective Optimization in Physical Synthesis of Integrated Circuits10.1007/978-1-4614-1356-1_6(83-103)Online publication date: 8-Aug-2012
https://doi.org/10.1007/978-1-4614-1356-1_6
Papa DMarkov IA. Papa DL. Markov I(2012)Buffer Insertion During Timing-Driven PlacementMulti-Objective Optimization in Physical Synthesis of Integrated Circuits10.1007/978-1-4614-1356-1_3(21-46)Online publication date: 8-Aug-2012
https://doi.org/10.1007/978-1-4614-1356-1_3
Papa DMarkov IA. Papa DL. Markov I(2012)State of the Art in Physical SynthesisMulti-Objective Optimization in Physical Synthesis of Integrated Circuits10.1007/978-1-4614-1356-1_2(11-18)Online publication date: 8-Aug-2012
https://doi.org/10.1007/978-1-4614-1356-1_2
Meyerov IKamaev AKornyakov KZhivoderov A(2010)Comparative analysis of effectiveness of two timing-driven design approachesProceedings of the Second Russia-Taiwan conference on Methods and tools of parallel programming multicomputers10.5555/1927517.1927555(277-282)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.5555/1927517.1927555
Li ZPapa DAlpert CHu SShi WSze CZhou YSaxena PChang Y(2010)Ultra-fast interconnect driven cell cloning for minimizing critical path delayProceedings of the 19th international symposium on Physical design10.1145/1735023.1735047(75-82)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.1145/1735023.1735047
Meyerov IKamaev AKornyakov KZhivoderov A(2010)Comparative Analysis of Effectiveness of Two Timing-Driven Design ApproachesMethods and Tools of Parallel Programming Multicomputers10.1007/978-3-642-14822-4_31(277-282)Online publication date: 2010
https://doi.org/10.1007/978-3-642-14822-4_31
Luo TPapa DLi ZSze CAlpert CPan DNassif SRoychowdhury J(2008)PyramidsProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509510(204-211)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509510
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