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A reconfigurable logic machine for fast event-driven simulation

Authors:

Jerry Bauer,

Michael Bershteyn,

Ian Kaplan,

Paul VyedinAuthors Info & Claims

DAC '98: Proceedings of the 35th annual Design Automation Conference

Pages 668 - 671

https://doi.org/10.1145/277044.277214

Published: 01 May 1998 Publication History

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Abstract

As the density of VLSI circuits increases, software techniques cannot effectively simulate designs through the millions of simulation cycles needed for verification. Emulation can supply the necessary capacity and performance, but emulation is limited to designs that are structural or can be synthesized. This paper discusses a new system architecture that dramatically accelerates event-driven behavioral simulation and describes how it is merged with emulation.

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A reconfigurable logic machine for fast event-driven simulation

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Published In

DAC '98: Proceedings of the 35th annual Design Automation Conference

May 1998

820 pages

ISBN:0897919645

DOI:10.1145/277044

Chairmen:
Basant R. Chawla
Lucent Technologies, Warren, NJ
,
Randal E. Bryant
Carnegie Mellon Univ., Pittsburgh, PA
,
Jan M. Rabaey
Univ. of California, Berkeley
,
Editor:
M. J. Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 May 1998

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DAC98

Sponsor:

EDAC
SIGDA
IEEE-CS

DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference

June 15 - 19, 1998

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Saha SDuwe HZambreno J(2020)CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural NetworksJournal of Signal Processing Systems10.1007/s11265-020-01546-xOnline publication date: 19-Jun-2020
https://doi.org/10.1007/s11265-020-01546-x
Saha SDuwe HZambreno J(2019)An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2019.000-2(197-205)Online publication date: Jul-2019
https://doi.org/10.1109/ASAP.2019.000-2
Chuang CLiu C(2011)Hybrid Testbench Acceleration for Reducing Communication OverheadIEEE Design & Test10.1109/MDT.2011.3328:2(40-51)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/MDT.2011.33
Ruan ALi CSong ZChen JDeng LHou HLiao Y(2011)The third generation verification technology based SOC debugging2011 International Conference on Computational Problem-Solving (ICCP)10.1109/ICCPS.2011.6092213(109-114)Online publication date: Oct-2011
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Becker ASirowy SVahid F(2011)Just-in-time compilation for FPGA processor cores2011 Electronic System Level Synthesis Conference (ESLsyn)10.1109/ESLsyn.2011.5952282(1-6)Online publication date: Jun-2011
https://doi.org/10.1109/ESLsyn.2011.5952282
Dusung Kim Ciesielski MSeiyang Yang (2011)A new distributed event-driven gate-level HDL simulation by accurate prediction2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763280(1-4)Online publication date: Mar-2011
https://doi.org/10.1109/DATE.2011.5763280
Dusung Kim Ciesielski MKyuho Shim Seiyang Yang (2011)Temporal parallel simulation: A fast gate-level HDL simulation using higher level models2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763251(1-6)Online publication date: Mar-2011
https://doi.org/10.1109/DATE.2011.5763251
Blumer APatterson C(2008)Exploiting process locality of reference in RTL simulation accelerationEURASIP Journal on Embedded Systems10.1155/2008/3690402008(1-10)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1155/2008/369040
Asadi GMiremadi SEjlali A(2007)Fast co-verification of HDL modelsMicroelectronic Engineering10.1016/j.mee.2006.02.00784:2(218-228)Online publication date: 1-Feb-2007
https://dl.acm.org/doi/10.1016/j.mee.2006.02.007
Chung MKim YLee JYang WKi AKyung C(2007)Soc Prototyping and VerificationEssential Issues in SOC Design10.1007/1-4020-5352-5_7(225-264)Online publication date: 2007
https://doi.org/10.1007/1-4020-5352-5_7
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