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Reducing power in high-performance microprocessors

Authors:

Franklin BaezAuthors Info & Claims

DAC '98: Proceedings of the 35th annual Design Automation Conference

Pages 732 - 737

https://doi.org/10.1145/277044.277227

Published: 01 May 1998 Publication History

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Abstract

Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.

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Cited By

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Chatzopoulos OTrakosa MPapadimitriou GWong WGizopoulos D(2024)SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00021(120-131)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00021
Ding JLu LFu ZMa JGong MQi YYu W(2023)Clock Aware Low Power Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323626(01-08)Online publication date: 28-Oct-2023
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Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
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Reducing power in high-performance microprocessors

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Published In

DAC '98: Proceedings of the 35th annual Design Automation Conference

May 1998

820 pages

ISBN:0897919645

DOI:10.1145/277044

Chairmen:
Basant R. Chawla
Lucent Technologies, Warren, NJ
,
Randal E. Bryant
Carnegie Mellon Univ., Pittsburgh, PA
,
Jan M. Rabaey
Univ. of California, Berkeley
,
Editor:
M. J. Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 01 May 1998

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DAC98

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EDAC
SIGDA
IEEE-CS

DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference

June 15 - 19, 1998

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Chatzopoulos OTrakosa MPapadimitriou GWong WGizopoulos D(2024)SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00021(120-131)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00021
Ding JLu LFu ZMa JGong MQi YYu W(2023)Clock Aware Low Power Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323626(01-08)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323626
Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
Ogbebor JImoize AAtayero A(2020)Energy Efficient Design Techniques in Next-Generation Wireless Communication NetworksWireless Communications & Mobile Computing10.1155/2020/72353622020Online publication date: 1-Jan-2020
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Martino RCilardo A(2020)SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative SurveyIEEE Access10.1109/ACCESS.2020.29722658(28415-28436)Online publication date: 2020
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Kumar NVidyarthi D(2020)A novel energy-efficient scheduling model for multi-core systemsCluster Computing10.1007/s10586-020-03143-w24:2(643-666)Online publication date: 29-Jun-2020
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Khan AAli AZakarya MKhan RKhan MRahman IRahman M(2019)A migration aware scheduling technique for real-time aperiodic tasks over multiprocessor systemsIEEE Access10.1109/ACCESS.2019.2901411(1-1)Online publication date: 2019
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Ted Dibene JHockanson D(2019)IntroductionPower Integrity for Electrical and Computer Engineers10.1002/9781119263364.ch1(1-20)Online publication date: 6-Sep-2019
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