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Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits

Authors:

Atila Alvandpour,

Per Larsson-Edefors,

Christer SvenssonAuthors Info & Claims

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

Pages 245 - 249

https://doi.org/10.1145/280756.280919

Published: 10 August 1998 Publication History

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Abstract

In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a V_dd close to V_T and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low V_dd.

To avoid reducing V_dd below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to V_T based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.

References

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Mert YSimsek O(2015)Employing dynamic body-bias for short circuit power reduction in SRAMsSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085437(267-271)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085437
Morgenshtein A(2012)Short-Circuit Power Reduction by Using High-Threshold TransistorsJournal of Low Power Electronics and Applications10.3390/jlpea20100692:1(69-78)Online publication date: 1-Mar-2012
https://doi.org/10.3390/jlpea2010069
Alipour SHidaji BPour A(2010)Circuit level, static power, and logic level power analyses2010 IEEE International Conference on Electro/Information Technology10.1109/EIT.2010.5612180(1-4)Online publication date: May-2010
https://doi.org/10.1109/EIT.2010.5612180
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Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits

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ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 August 1998

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ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

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Mert YSimsek O(2015)Employing dynamic body-bias for short circuit power reduction in SRAMsSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085437(267-271)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085437
Morgenshtein A(2012)Short-Circuit Power Reduction by Using High-Threshold TransistorsJournal of Low Power Electronics and Applications10.3390/jlpea20100692:1(69-78)Online publication date: 1-Mar-2012
https://doi.org/10.3390/jlpea2010069
Alipour SHidaji BPour A(2010)Circuit level, static power, and logic level power analyses2010 IEEE International Conference on Electro/Information Technology10.1109/EIT.2010.5612180(1-4)Online publication date: May-2010
https://doi.org/10.1109/EIT.2010.5612180
Pedram MNazarian S(2006)Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and MethodsProceedings of the IEEE10.1109/JPROC.2006.87979794:8(1487-1501)Online publication date: Aug-2006
https://doi.org/10.1109/JPROC.2006.879797
Solomatnikov ASomasekhar DSirisantana NRoy K(2002)Skewed CMOSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80051910:4(469-476)Online publication date: 1-Aug-2002
https://dl.acm.org/doi/10.1109/TVLSI.2002.800519
(2002)Power Analysis for CMOS CircuitsElectrothermal Analysis of VLSI Systems10.1007/0-306-47024-1_2(21-43)Online publication date: 2002
https://doi.org/10.1007/0-306-47024-1_2
Joshi RHuang WChuang CRoy KKang SKoh C(2001)SOI for asynchronous dynamic circuitsProceedings of the 11th Great Lakes symposium on VLSI10.1145/368122.368734(37-42)Online publication date: 1-Mar-2001
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Rui Wang Roy KCheng-Kok Koh (2001)Short-circuit power analysis of an inverter driving an RLC loadISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)10.1109/ISCAS.2001.922380(886-889)Online publication date: 2001
https://doi.org/10.1109/ISCAS.2001.922380
Stan M(2001)Low-power CMOS with supply voltagesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.9240629:2(394-400)Online publication date: 1-Apr-2001
https://dl.acm.org/doi/10.1109/92.924062
Joshi RHwang WWilson SChuang C(2000)"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology (poster session)Proceedings of the 2000 international symposium on Low power electronics and design10.1145/344166.344586(203-206)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1145/344166.344586
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A power modeling and characterization method for the CMOS standard cell library

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A power modeling and characterization method for the CMOS standard cell library

Various Low Power Approaches in CMOS Vlsi Circuits

Managing power constraints in a single-core scenario through power tokens

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