short-paper

A Case for Work-stealing on FPGAs with OpenCL Atomics

Authors:

Nadesh Ramanathan,

John Wickerson,

Felix Winterstein,

George A. ConstantinidesAuthors Info & Claims

FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 48 - 53

https://doi.org/10.1145/2847263.2847343

Published: 21 February 2016 Publication History

Abstract

We provide a case study of work-stealing, a popular method for run-time load balancing, on FPGAs. Following the Cederman-Tsigas implementation for GPUs, we synchronize work-items not with locks, mutexes or critical sections, but instead with the atomic operations provided by Altera's OpenCL SDK. We evaluate work-stealing for FPGAs by synthesizing a K-means clustering algorithm on an Altera P385 D5 board, both with work-stealing and with a statically-partitioned load. When block RAM utilization is maximised in both cases, we find that work-stealing leads to a 1.5x speedup. This demonstrates that the ability to do load balancing at run-time can outweigh the drawback of using `expensive' atomics on FPGAs. We hope that our case study will stimulate further research into the high-level synthesis of fine-grained, lock-free, concurrent programs.

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Cited By

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https://doi.org/10.1109/FCCM60383.2024.00025
Garzón ELanuzza MTeman AYavits L(2023) AM 4 : MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing IEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324322213:1(408-421)Online publication date: Mar-2023
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Yavits L(2023)Will computing in memory become a new dawn of associative processors?Memories - Materials, Devices, Circuits and Systems10.1016/j.memori.2023.1000334(100033)Online publication date: Jul-2023
https://doi.org/10.1016/j.memori.2023.100033
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Index Terms

A Case for Work-stealing on FPGAs with OpenCL Atomics

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Published In

cover image ACM Conferences

FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2016

298 pages

ISBN:9781450338561

DOI:10.1145/2847263

General Chair:
Deming Chen
University of Illinois at Urbana-Champaign, USA
,
Program Chair:
Jonathan Greene
Microsemi, USA

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 21 February 2016

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Short-paper

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Engineering and Physical Sciences Research Council

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FPGA'16

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SIGDA

FPGA'16: The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 21 - 23, 2016

California, Monterey, USA

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FPGA '16 Paper Acceptance Rate 20 of 111 submissions, 18%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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https://doi.org/10.1109/FCCM60383.2024.00025
Garzón ELanuzza MTeman AYavits L(2023) AM 4 : MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing IEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324322213:1(408-421)Online publication date: Mar-2023
https://doi.org/10.1109/JETCAS.2023.3243222
Yavits L(2023)Will computing in memory become a new dawn of associative processors?Memories - Materials, Devices, Circuits and Systems10.1016/j.memori.2023.1000334(100033)Online publication date: Jul-2023
https://doi.org/10.1016/j.memori.2023.100033
Chen XCheng FTan HChen YHe BWong WChen D(2022)ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLSACM Transactions on Reconfigurable Technology and Systems10.1145/351714115:4(1-31)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3517141
Yavits LKaplan RGinosar R(2022)GIRAF: General Purpose In-Storage Resistive Associative FrameworkIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.306544833:2(276-287)Online publication date: 1-Feb-2022
https://doi.org/10.1109/TPDS.2021.3065448
Zhang FZheng LLiao XLv XJin HXiao J(2022)An Effective 2-Dimension Graph Partitioning for Work Stealing Assisted Graph Processing on Multi-FPGAsIEEE Transactions on Big Data10.1109/TBDATA.2020.30350908:5(1247-1258)Online publication date: 1-Oct-2022
https://doi.org/10.1109/TBDATA.2020.3035090
Iorga DDonaldson ASorensen TWickerson J(2021)The semantics of shared memory in Intel CPU/FPGA systemsProceedings of the ACM on Programming Languages10.1145/34854975:OOPSLA(1-28)Online publication date: 15-Oct-2021
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Chen XTan HChen YHe BWong WChen DShannon LAdler M(2021)ThunderGPThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439290(69-80)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439290
Jin ZVetter J(2021)Evaluating the Performance of Integer Sum Reduction on an Intel GPU2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW52791.2021.00099(652-655)Online publication date: Jun-2021
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Chen XTan HChen YHe BWong WChen D(2021)Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586184(937-942)Online publication date: 5-Dec-2021
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