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Maximizing Performance Under a Power Cap: A Comparison of Hardware, Software, and Hybrid Techniques

Published: 25 March 2016 Publication History

Abstract

Power and thermal dissipation constrain multicore performance scaling. Modern processors are built such that they could sustain damaging levels of power dissipation, creating a need for systems that can implement processor power caps. A particular challenge is developing systems that can maximize performance within a power cap, and approaches have been proposed in both software and hardware. Software approaches are flexible, allowing multiple hardware resources to be coordinated for maximum performance, but software is slow, requiring a long time to converge to the power target. In contrast, hardware power capping quickly converges to the the power cap, but only manages voltage and frequency, limiting its potential performance. In this work we propose PUPiL, a hybrid software/hardware power capping system. Unlike previous approaches, PUPiL combines hardware's fast reaction time with software's flexibility. We implement PUPiL on real Linux/x86 platform and compare it to Intel's commercial hardware power capping system for both single and multi-application workloads. We find PUPiL provides the same reaction time as Intel's hardware with significantly higher performance. On average, PUPiL outperforms hardware by from 1:18-2:4 depending on workload and power target. Thus, PUPiL provides a promising way to enforce power caps with greater performance than current state-of-the-art hardware-only approaches.

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cover image ACM Conferences
ASPLOS '16: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems
March 2016
824 pages
ISBN:9781450340915
DOI:10.1145/2872362
  • General Chair:
  • Tom Conte,
  • Program Chair:
  • Yuanyuan Zhou
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Published: 25 March 2016

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  1. adaptive systems
  2. decision-tree
  3. power management

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  • Dept. of Energy
  • NSF

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ASPLOS '16 Paper Acceptance Rate 53 of 232 submissions, 23%;
Overall Acceptance Rate 535 of 2,713 submissions, 20%

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Cited By

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  • (2024)Process-Based Efficient Power Level Exporter2024 IEEE 17th International Conference on Cloud Computing (CLOUD)10.1109/CLOUD62652.2024.00058(456-467)Online publication date: 7-Jul-2024
  • (2024)Investigation of Performance and Energy Consumption of Tokenization Algorithms on Multi-core CPUs Under Power CappingComputer Information Systems and Industrial Management10.1007/978-3-031-71115-2_23(332-346)Online publication date: 27-Sep-2024
  • (2024)Dynamic Tuning of Core Counts to Maximize Performance in Object-Based Runtime SystemsAsynchronous Many-Task Systems and Applications10.1007/978-3-031-61763-8_9(92-104)Online publication date: 30-May-2024
  • (2023)Challenges and Opportunities in Sustainable Serverless ComputingACM SIGEnergy Energy Informatics Review10.1145/3630614.36306243:3(53-58)Online publication date: 25-Oct-2023
  • (2022)TokenSmart: Distributed, Scalable Power Management in the Many-core EraACM Transactions on Architecture and Code Optimization10.1145/355976220:1(1-26)Online publication date: 17-Nov-2022
  • (2022)Adaptive Power Shifting for Power-Constrained Heterogeneous SystemsIEEE Transactions on Computers10.1109/TC.2022.3174545(1-1)Online publication date: 2022
  • (2022)Future aware Dynamic Thermal Management in CPU-GPU Embedded Platforms2022 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS55097.2022.00041(396-408)Online publication date: Dec-2022
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  • (2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server ApplicationsProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00063(835-850)Online publication date: 1-Oct-2022
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