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Gate-size selection for standard cell libraries

Authors:

Frederik Beeftink,

Prabhakar Kudva,

David Kung,

Leon StokAuthors Info & Claims

ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Pages 545 - 550

https://doi.org/10.1145/288548.289084

Published: 01 November 1998 Publication History

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Melikyan VMelikyan V(2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
https://doi.org/10.1007/978-3-031-50714-4_6
Madhavan SPhadke RN B(2021)Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System2021 International Conference on Circuits, Controls and Communications (CCUBE)10.1109/CCUBE53681.2021.9702732(1-6)Online publication date: 23-Dec-2021
https://doi.org/10.1109/CCUBE53681.2021.9702732
Lim SLim YMashohor SKamsani NSidek RHashim SRokhani F(2017)Generating power-optimal standard cell library specification using neural network technique2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)10.1109/PRIMEASIA.2017.8280374(101-104)Online publication date: Oct-2017
https://doi.org/10.1109/PRIMEASIA.2017.8280374
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Gate-size selection for standard cell libraries

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ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

November 1998

704 pages

ISBN:1581130082

DOI:10.1145/288548

Chairman:
Hiroto Yasuura
Kyushu Univ., Fukuoka, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 November 1998

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ICCAD '98: International Conference on Computer-Aided Design - 1998

November 8 - 12, 1998

California, San Jose, USA

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Melikyan VMelikyan V(2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
https://doi.org/10.1007/978-3-031-50714-4_6
Madhavan SPhadke RN B(2021)Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System2021 International Conference on Circuits, Controls and Communications (CCUBE)10.1109/CCUBE53681.2021.9702732(1-6)Online publication date: 23-Dec-2021
https://doi.org/10.1109/CCUBE53681.2021.9702732
Lim SLim YMashohor SKamsani NSidek RHashim SRokhani F(2017)Generating power-optimal standard cell library specification using neural network technique2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)10.1109/PRIMEASIA.2017.8280374(101-104)Online publication date: Oct-2017
https://doi.org/10.1109/PRIMEASIA.2017.8280374
Khatri SShenoy NGiomi JKhouja A(2016)Logic SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-4(27-55)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-4
Fabrie SEcheverri JVertregt Mde Gyvez JFettweis GNebel W(2014)Standard cell library tuning for variability tolerant designsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616886(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616886
Ren HDutt S(2013)Fast and near-optimal timing-driven cell sizing under cell area and leakage power constraints using a simplified discrete network flow algorithmVLSI Design10.1155/2013/4746012013(1-1)Online publication date: 1-Jan-2013
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Orzan ABousseau ABarla PWinnemöller HThollot JSalesin D(2013)Diffusion curvesCommunications of the ACM10.1145/2483852.248387356:7(101-108)Online publication date: 1-Jul-2013
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MCML Gate Design for Standard Cell Library

Optimising variability tolerant standard cell libraries

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

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MCML Gate Design for Standard Cell Library

Optimising variability tolerant standard cell libraries

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

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