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R-GPU: A Reconfigurable GPU Architecture

Published: 07 March 2016 Publication History

Abstract

Over the last decade, Graphics Processing Unit (GPU) architectures have evolved from a fixed-function graphics pipeline to a programmable, energy-efficient compute accelerator for massively parallel applications. The compute power arises from the GPU’s Single Instruction/Multiple Threads architecture: concurrently running many threads and executing them as Single Instruction/Multiple Data--style vectors. However, compute power is still lost due to cycles spent on data movement and control instructions instead of data computations. Even more cycles are lost on pipeline stalls resulting from long latency (memory) operations.
To improve not only performance but also energy efficiency, we introduce R-GPU: a reconfigurable GPU architecture with communicating cores. R-GPU is an addition to a GPU, which can still be used as such, but also has the ability to reorganize the cores of a GPU in a reconfigurable network. In R-GPU data movement and control is implicit in the configuration of the network. Each core executes a fixed instruction, reducing instruction decode count and increasing energy efficiency. On a number of benchmarks we show an average performance improvement of 2.1 × over the same GPU without modifications. We further make a conservative power estimation of R-GPU which shows that power consumption can be reduced by 6%, leading to an energy consumption reduction of 55%, while area only increases by a mere 4%.

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  • (2018)Elastic Search in Cache Based Service Management For Healthcare Automation2018 International Conference on Advances in Computing and Communication Engineering (ICACCE)10.1109/ICACCE.2018.8441722(445-450)Online publication date: Jun-2018
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Published In

cover image ACM Transactions on Architecture and Code Optimization
ACM Transactions on Architecture and Code Optimization  Volume 13, Issue 1
April 2016
347 pages
ISSN:1544-3566
EISSN:1544-3973
DOI:10.1145/2899032
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 March 2016
Accepted: 01 February 2016
Revised: 01 December 2015
Received: 01 May 2015
Published in TACO Volume 13, Issue 1

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Author Tags

  1. GPGPU
  2. reconfigurable architecture

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Cited By

View all
  • (2018)Inter-thread communication in multithreaded, reconfigurable coarse-grain arraysProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00013(42-54)Online publication date: 20-Oct-2018
  • (2018)Elastic Search in Cache Based Service Management for Healthcare Automation2018 International Conference on Communications (COMM)10.1109/ICComm.2018.8430162(01-06)Online publication date: 14-Jun-2018
  • (2018)Elastic Search in Cache Based Service Management For Healthcare Automation2018 International Conference on Advances in Computing and Communication Engineering (ICACCE)10.1109/ICACCE.2018.8441722(445-450)Online publication date: Jun-2018
  • (2017)Design of a dynamically reconfigurable architecture for the 3D image synthesis2017 International Conference on Advanced Technologies for Signal and Image Processing (ATSIP)10.1109/ATSIP.2017.8075556(1-5)Online publication date: May-2017

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