research-article

Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators

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DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 136, Pages 1 - 6

https://doi.org/10.1145/2897937.2898040

Published: 05 June 2016 Publication History

Abstract

The increasing complexity of FPGA-based accelerators, coupled with time-to-market pressure, makes high-level synthesis (HLS) an attractive solution to improve designer productivity by abstracting the programming effort above register-transfer level (RTL). HLS offers various architectural design options with different trade-offs via pragmas (loop unrolling, loop pipelining, array partitioning). However, non-negligible HLS runtime renders manual or automated HLS-based exhaustive architectural exploration practically infeasible. To address this challenge, we present Lin-Analyzer, a high-level accurate performance analysis tool that enables rapid design space exploration with various pragmas for FPGA-based accelerators without requiring RTL implementations.

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Cited By

Pouget SPouchet LCong J(2025)Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming ApproachACM Transactions on Design Automation of Electronic Systems10.1145/371184730:2(1-44)Online publication date: 7-Feb-2025
https://dl.acm.org/doi/10.1145/3711847
Ferikoglou AKakolyris AMasouros DSoudris DXydis S(2024)CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design OptimizationACM Transactions on Reconfigurable Technology and Systems10.1145/370200518:1(1-32)Online publication date: 26-Oct-2024
https://dl.acm.org/doi/10.1145/3702005
Zhang MZhang ZNiu YLi JChen ZLi GHa YChen T(2024)Fast Constraints Tuning via Transfer Learning and Multiobjective OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337716243:9(2705-2718)Online publication date: Sep-2024
https://doi.org/10.1109/TCAD.2024.3377162
Show More Cited By

Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators
1. Hardware
  1. Electronic design automation

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2016

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Singapore Ministry of Education Academic Research Fund Tier 2

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Pouget SPouchet LCong J(2025)Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming ApproachACM Transactions on Design Automation of Electronic Systems10.1145/371184730:2(1-44)Online publication date: 7-Feb-2025
https://dl.acm.org/doi/10.1145/3711847
Ferikoglou AKakolyris AMasouros DSoudris DXydis S(2024)CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design OptimizationACM Transactions on Reconfigurable Technology and Systems10.1145/370200518:1(1-32)Online publication date: 26-Oct-2024
https://dl.acm.org/doi/10.1145/3702005
Zhang MZhang ZNiu YLi JChen ZLi GHa YChen T(2024)Fast Constraints Tuning via Transfer Learning and Multiobjective OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337716243:9(2705-2718)Online publication date: Sep-2024
https://doi.org/10.1109/TCAD.2024.3377162
Knorst TJordan MKorol GRutzig MBeck A(2024)An Automatic Framework for Collaborative CPU Thread Throttling and FPGA HLS-Versioning2024 XIV Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC65055.2024.10771920(1-6)Online publication date: 26-Nov-2024
https://doi.org/10.1109/SBESC65055.2024.10771920
Shang LWang TGong LWang CZhou X(2024)Enhancing HLS Performance Prediction on FPGAs Through Multimodal Representation LearningIEEE Embedded Systems Letters10.1109/LES.2024.344679716:4(385-388)Online publication date: Dec-2024
https://doi.org/10.1109/LES.2024.3446797
Parchamdar BCarrion Schaefer B(2024)Investigating the Effect of Hyper-Parameter Settings on Simulated Annealing-Based High-Level Synthesis Design Space Exploration2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS)10.1109/DCAS61159.2024.10539862(1-5)Online publication date: 19-Apr-2024
https://doi.org/10.1109/DCAS61159.2024.10539862
Taghipour PGranger EBlaquière Y(2024)Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space ExplorationIEEE Access10.1109/ACCESS.2024.350960612(189574-189589)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3509606
Yao YHong HWang SXiao C(2024)Decomposition based estimation of distribution algorithm for high-level synthesis design space explorationIntegration10.1016/j.vlsi.2024.102292(102292)Online publication date: Oct-2024
https://doi.org/10.1016/j.vlsi.2024.102292
Bannwart Perina ABecker JBonato V(2024)Memory Aware Design Optimisation for High-Level SynthesisJournal of Signal Processing Systems10.1007/s11265-024-01938-396:11(651-671)Online publication date: 23-Dec-2024
https://doi.org/10.1007/s11265-024-01938-3
Lin CYi Y(2024)Enhancing FPGA CAD Flow with AI-Powered SolutionsAI-Enabled Electronic Circuit and System Design10.1007/978-3-031-71436-8_7(225-256)Online publication date: 17-Oct-2024
https://doi.org/10.1007/978-3-031-71436-8_7
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