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VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency

Published: 05 June 2016 Publication History

Abstract

A voltage regulator (VR) for a processor is one of the most critical platform components. Particularly, a VR is required to support fast, accurate, and fine-grained voltage changes for efficient processor power management. Such requirements, nonetheless, can be relaxed when a processor consumes low power at runtime. Thus, manufacturers begin to offer some knobs so that a processor can adapt VR's operating parameters to cost-effectively satisfy the requirements with high efficiency. In this paper, we first demonstrate that: (1) VR efficiency heavily depends on load current (i.e., current delivered to a processor) and a VR operating parameter (e.g., the number of active phases) at given voltage; (2) a processor running a parallel application mostly consumes small current due to aggressive power management; and (3) when the processor is in active state, all the phases are always activated in the VR. (2) and (3) in turn lead to poor VR efficiency at most runtime. Second, we present VR-Scale that dynamically scales the number of active phases based on the predicted load current for the next interval. Our evaluations based on an Intel processor running emerging parallel applications show that VR-Scale can reduce the total power consumed by a processor and its VR by more than 19% with negligible performance impact.

References

[1]
S. Pawlowski, "Driving Towards Cloud 2015: A technology Vision to Meet the Demands of Cloud Computing Tomorrow," 2011.
[2]
Intel Corporation, "Intel Workstation Board S975XBX2 Technical Product Specification," 2006.
[3]
X. Zhou, et al., "Investigation of Candidate VRM Topologies for Future Microprocessors," in IEEE Applied Power Electronics Conf. and Expo. (APEC), 1998.
[4]
Intel Corporation, {Online}. Available: http://www.intel.com/content/www/us/en/servers/technologies/efficie nt-power.html.
[5]
HP, Power efficiency and power management in HP ProLiant servers.
[6]
Intel Corporation, VR12/IMVP7 Pulse Width Modulation (PWM) Specification, 2009.
[7]
Intersil, "ISL6367 Green Hybrid Digital Dual 6+1 Phase PWM Controller for VR12/IMVP7 Applications With SMBus/PMBus/I2C and AUTO Phase."
[8]
ST, "PM6764, PM6766 VR12.5 digital multiphase controller with PMBus."
[9]
{Online}. Available: http://www.acpi.info/.
[10]
X. Zhou, et al., "A Novel Current-sharing Control Technique for Low-voltage High-current Voltage Regulator Module Applications," IEEE T. on Power Electronics, vol. 15, no. 6, pp. 1153--1162, Nov 2000.
[11]
ON Semiconductor, "Programmable Multi-Phase Synchronous Buck Converter," 2008.
[12]
J. Lee, et al., "Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies," IEEE T. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 9, pp. 1017--1027, Sep 2007.
[13]
International Rectifier, {Online}. Available: http://www.irf.com/technicalinfo/whitepaper/pswus03vrmdesign.pdf.
[14]
Texas Instrument, {Online}. Available: http://www.ti.com/product/TPS51631/technicaldocuments.
[15]
{Online}. Available: https://pmbus.org.
[16]
Princeton University, {Online}. Available: http://parsec.cs.princeton.edu/.
[17]
Z. Jia, et al., "Characterizing Data Analysis Workloads in Data Centers," in IEEE Int. Symp. on Workload Characterization (IISWC), 2013.
[18]
Standard Performance Evaluation Corporation, "SPEC CPU2006," 2006.
[19]
A. Jaleel, et al., "Adaptive Insertion Policies for Managing Shared Caches," in ACM Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2008.
[20]
J. Demme and S. Sethumadhavan, "Rapid Identification of Architectural Bottlenecks via Precise Event Counting," in IEEE/ACM Int. Symp. on Computer Architecture (ISCA), 2011.
[21]
V. Spiliopoulos, et al., "Power-Sleuth: A Tool for Investigating your Program's Power Behavior," in Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOT), 2012.
[22]
J. Jenne, "Dynamic CPU Voltage Regulator Phase Shedding". U.S.A. Patent US20110320838 A1, Dec 2011.
[23]
D. Freeman, "Digital Power Control Improves Multiphase Performance," Power Electronics Technology, pp. 2--3, Dec 2007.

Cited By

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  • (2020)Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex ModelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289483539:3(686-699)Online publication date: Mar-2020
  • (2020)FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00088(1051-1066)Online publication date: Oct-2020
  • (2019) An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285924838:9(1661-1674)Online publication date: Sep-2019
  • Show More Cited By

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cover image ACM Other conferences
DAC '16: Proceedings of the 53rd Annual Design Automation Conference
June 2016
1048 pages
ISBN:9781450342360
DOI:10.1145/2897937
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 June 2016

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View all
  • (2020)Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex ModelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289483539:3(686-699)Online publication date: Mar-2020
  • (2020)FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00088(1051-1066)Online publication date: Oct-2020
  • (2019) An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285924838:9(1661-1674)Online publication date: Sep-2019
  • (2018)Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297285(70-75)Online publication date: Jan-2018

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