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An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions

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Bill HardingAuthors Info & Claims

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

Pages 17 - 26

https://doi.org/10.1145/296399.296422

Published: 01 February 1999 Publication History

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Cited By

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Meyer JKocan F(2018)Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89358115:2(182-195)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2007.893581
Ahmed ERose J(2018)The effect of LUT and cluster size on deep-submicron FPGA performance and densityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82430012:3(288-298)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2004.824300
Marquardt ABetz VRose J(2018)Speed and area tradeoffs in cluster-based FPGA architecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.8207648:1(84-93)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/92.820764
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An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions
1. Hardware

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FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

February 1999

257 pages

ISBN:1581130880

DOI:10.1145/296399

Chairmen:
Sinan Kaptanoglu
Actel Corporation
,
Steve Trimberger
Xilinx

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Published: 01 February 1999

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FPGA99

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SIGDA

FPGA99: ACM/SIGDA Symposium on Field Programmable Gate Arrays

February 21 - 23, 1999

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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Meyer JKocan F(2018)Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89358115:2(182-195)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2007.893581
Ahmed ERose J(2018)The effect of LUT and cluster size on deep-submicron FPGA performance and densityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82430012:3(288-298)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2004.824300
Marquardt ABetz VRose J(2018)Speed and area tradeoffs in cluster-based FPGA architecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.8207648:1(84-93)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/92.820764
Lin MHutton MChow P(2008)The amorphous FPGA architectureProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344700(191-200)Online publication date: 24-Feb-2008
https://dl.acm.org/doi/10.1145/1344671.1344700
Kocan FMeyer J(2004)Logic Modules with Shared SRAM Tables for Field-Programmable Gate ArraysField Programmable Logic and Application10.1007/978-3-540-30117-2_31(289-300)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30117-2_31
Beckett P(2002)A fine-grained reconfigurable logic array based on double gate transistors2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.10.1109/FPT.2002.1188690(260-267)Online publication date: 2002
https://doi.org/10.1109/FPT.2002.1188690
Ahmed ERose JTrimberger SHauck S(2000)The effect of LUT and cluster size on deep-submicron FPGA performance and densityProceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays10.1145/329166.329171(3-12)Online publication date: 1-Feb-2000
https://dl.acm.org/doi/10.1145/329166.329171

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