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Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density

Authors:

Alexander (Sandy) Marquardt,

Vaughn Betz, and

Jonathan RoseAuthors Info & Claims

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

February 1999

Pages 37 - 46

https://doi.org/10.1145/296399.296426

Published: 01 February 1999 Publication History

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Li ZZhu ZHe HChen J(2024)An effective routability-driven packing algorithm for large-scale heterogeneous FPGAsIntegration10.1016/j.vlsi.2023.10209894(102098)Online publication date: Jan-2024
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Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
1. Hardware

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Published In

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

February 1999

257 pages

ISBN:1581130880

DOI:10.1145/296399

Chairmen:
Sinan Kaptanoglu
Actel Corporation
,
Steve Trimberger
Xilinx

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 February 1999

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FPGA99

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SIGDA

FPGA99: ACM/SIGDA Symposium on Field Programmable Gate Arrays

February 21 - 23, 1999

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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https://dl.acm.org/doi/10.1145/3639055
Li ZZhu ZHe HChen J(2024)An effective routability-driven packing algorithm for large-scale heterogeneous FPGAsIntegration10.1016/j.vlsi.2023.10209894(102098)Online publication date: Jan-2024
https://doi.org/10.1016/j.vlsi.2023.102098
Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Physical ImplementationFPGA EDA10.1007/978-981-99-7755-0_10(165-206)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_10
Yu LGuo BZhi TBai L(2023)Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural NetworksElectronics10.3390/electronics1212269112:12(2691)Online publication date: 15-Jun-2023
https://doi.org/10.3390/electronics12122691
Taj IFarooq U(2023)Towards Machine Learning-Based FPGA Backend Flow: Challenges and OpportunitiesElectronics10.3390/electronics1204093512:4(935)Online publication date: 13-Feb-2023
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https://doi.org/10.1109/FPL60245.2023.00016
Rostami-Sani SRazzaq AYe A(2022)Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM53951.2022.9786176(1-9)Online publication date: 15-May-2022
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