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Scaling Data Analytics with Moore's Law

Published: 11 September 2016 Publication History

Abstract

Analyzing the volume, variety and velocity of big data requires the use of modern heterogeneous computing platforms composed of multicores with SIMD execution units, GPUs, clusters, FPGAs and in the future new reconfigurable architectures. However, programming in this environment is extremely challenging due to the need to use multiple low-level programming models and then combine them together in ad-hoc ways. Furthermore, many data analytics algorithms do not take full advantage of modern hardware capabilities. To optimize big data applications both for modern hardware and for modern programmers needs algorithms specialized for modern hardware and a high-level programming model that executes efficiently on heterogeneous parallel hardware. In this talk, I will describe the Delite DSL framework, which uses nested parallel patterns encapsulated in domain specific languages (DSLs). I will describe how a nested parallel pattern based programming model can be used to develop new data analytics algorithms that are optimized for architectures as diverse as multicore/NUMA, clusters, GPUs, FPGAs and a new reconfigurable architecture called Plasticine.

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  1. Scaling Data Analytics with Moore's Law

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    cover image ACM Conferences
    PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation
    September 2016
    474 pages
    ISBN:9781450341219
    DOI:10.1145/2967938
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 11 September 2016

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    • Invited-talk

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    PACT '16
    Sponsor:
    • IFIP WG 10.3
    • IEEE TCCA
    • SIGARCH
    • IEEE CS TCPP

    Acceptance Rates

    PACT '16 Paper Acceptance Rate 31 of 119 submissions, 26%;
    Overall Acceptance Rate 121 of 471 submissions, 26%

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