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Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud

Published: 03 October 2016 Publication History
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  • Abstract

    With the nature of being memory hungry, in-memory key-value store is fundamentally subject to very high memory cost and energy consumption. Intuitively, the availability of a strong memory error correction at sufficiently small redundancy overhead could be leveraged to reduce memory cost and/or energy consumption. Nevertheless, current computing systems handle memory error correction solely in the hardware stack with very weak error correction strength. This paper for the first time studies the practical feasibility of implementing strong memory error correction code (ECC) in the software stack for in-memory key-value store without incurring significant speed performance penalty. This is fundamentally enabled by the low memory bandwidth utilization and relatively simple data structure of in-memory key-value store, which are actually shared with many other datacenter applications (e.g., Web search). This paper presents several design techniques to optimize software-based ECC implementation for in-memory key-value store, and elaborates on several important design issues. Using Memcached and RAMCloud as test vehicles, this work shows that the proposed design solution can improve the memory error correction strength by several orders of magnitude at similar (and even less) coding redundancy compared with current hardware-based design practice, and meanwhile incur less than 6% degradation of in-memory key-value store operational throughput.

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    Cited By

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    • (2024)Supports for Testing Memory Error Handling Code of In-memory Key Value Stores2024 19th European Dependable Computing Conference (EDCC)10.1109/EDCC61798.2024.00020(41-48)Online publication date: 8-Apr-2024
    • (2022)Graceful ECC-uncorrectable Error Handling in the Operating System Kernel2022 IEEE 33rd International Symposium on Software Reliability Engineering (ISSRE)10.1109/ISSRE55969.2022.00021(109-120)Online publication date: Oct-2022
    • (2022)Hardening In-memory Key-value Stores against ECC-uncorrectable Memory Errors2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN53405.2022.00057(509-521)Online publication date: Jun-2022

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    cover image ACM Other conferences
    MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems
    October 2016
    463 pages
    ISBN:9781450343053
    DOI:10.1145/2989081
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 03 October 2016

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    Author Tags

    1. Error Correction
    2. In-memory Key-value Store
    3. Memory Fault Tolerance

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    • (2024)Supports for Testing Memory Error Handling Code of In-memory Key Value Stores2024 19th European Dependable Computing Conference (EDCC)10.1109/EDCC61798.2024.00020(41-48)Online publication date: 8-Apr-2024
    • (2022)Graceful ECC-uncorrectable Error Handling in the Operating System Kernel2022 IEEE 33rd International Symposium on Software Reliability Engineering (ISSRE)10.1109/ISSRE55969.2022.00021(109-120)Online publication date: Oct-2022
    • (2022)Hardening In-memory Key-value Stores against ECC-uncorrectable Memory Errors2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN53405.2022.00057(509-521)Online publication date: Jun-2022

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