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On-board non-regression test of HLS tools targeting FPGA

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Arif SasongkoAuthors Info & Claims

RSP '16: Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype

Pages 41 - 47

https://doi.org/10.1145/2990299.2990307

Published: 01 October 2016 Publication History

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Abstract

High-Level Synthesis (HLS) has opened an opportunity for software programmers to target FPGA more rapidly. When developing HLS tools, tests are desirable to ensure their function, reliability and performance. When modifications are applied to a tool, Non-Regression Test (NRT) asserts that the changes have intended effect while Regression Test (RT) verifies that the tool still performs correctly without unwanted behaviour.

The work presented in this paper is focused on a method to automatically perform Non-Regression Test in HLS tool developments, although it can also be used as a Regression Testing technique. This method relies on a framework which allows HLS tool developers to verify the circuits generated from the tool directly on FPGA, instead of using simulations. The verification flow is automatic, so that knowing the details of the system is unnecessary for developers. The framework has been tested successfully over several applications from HLS benchmark and it gives more promising results than its simulation counterpart.

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Caba JRincon FBarba JDe La Torre JDondo JLopez J(2021)Towards Test-Driven Development for FPGA-based Modules Across Abstraction LevelsIEEE Access10.1109/ACCESS.2021.3059941(1-1)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3059941
Caba JRincón FDondo JBarba JAbaldea MLópez J(2019)Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlaysIntegration, the VLSI Journal10.1016/j.vlsi.2019.06.01168:C(129-138)Online publication date: 1-Sep-2019
https://dl.acm.org/doi/10.1016/j.vlsi.2019.06.011
Caba JCardoso JRincón FDondo JLópez J(2018)Rapid Prototyping and Verification of Hardware Modules Generated Using HLSApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_36(446-458)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_36

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On-board non-regression test of HLS tools targeting FPGA
1. Hardware

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RSP '16: Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype

October 2016

141 pages

ISBN:9781450345354

DOI:10.1145/2990299

Program Chairs:
Kenneth Kent
University of New Brunswick, Canada
,
Sungjoo Yoo
Seoul National University, South Korea

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 October 2016

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Caba JRincon FBarba JDe La Torre JDondo JLopez J(2021)Towards Test-Driven Development for FPGA-based Modules Across Abstraction LevelsIEEE Access10.1109/ACCESS.2021.3059941(1-1)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3059941
Caba JRincón FDondo JBarba JAbaldea MLópez J(2019)Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlaysIntegration, the VLSI Journal10.1016/j.vlsi.2019.06.01168:C(129-138)Online publication date: 1-Sep-2019
https://dl.acm.org/doi/10.1016/j.vlsi.2019.06.011
Caba JCardoso JRincón FDondo JLópez J(2018)Rapid Prototyping and Verification of Hardware Modules Generated Using HLSApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_36(446-458)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_36

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Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration

Bit-level optimization for high-level synthesis and FPGA-based acceleration

Hardware Coprocessor Synthesis from an ANSI C Specification

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Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration

Bit-level optimization for high-level synthesis and FPGA-based acceleration

Hardware Coprocessor Synthesis from an ANSI C Specification

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