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Clock Tree Construction based on Arrival Time Constraints

Authors:

Cheng-Kok KohAuthors Info & Claims

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

Pages 67 - 74

https://doi.org/10.1145/3036669.3036671

Published: 19 March 2017 Publication History

Abstract

There are striking differences between constructing clock trees based on dynamic implied skew constraints and based on static arrival time constraints. Dynamic implied skew constraints allow the full timing margins to be utilized, but the constraints are required to be updated (with high time complexity). In contrast, static arrival time constraints are decoupled and are not required to be updated. Therefore, the constraints can be obtained in constant time, which facilitates the exploration of various tree topologies. On the other hand, arrival time constraints do not allow the full timing margins to be utilized. Consequently, there is a trade-off between topology exploration and timing margin utilization. In this paper, the advantages of static arrival time constraints are leveraged to construct clock trees with useful skew while exploring various tree topologies. Moreover, the constraints are specified and respecified throughout the synthesis process reduce the cost of the constructed clock trees. It is experimentally demonstrated that the proposed approach results in clock trees with 16% lower average capacitive cost compared with clock trees constructed based on dynamic implied skew constraints.

References

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Cited By

Vanna-Iampikul PLu YShim DLim S(2023)GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICsACM Transactions on Design Automation of Electronic Systems10.1145/358857028:5(1-26)Online publication date: 6-Apr-2023
https://dl.acm.org/doi/10.1145/3588570
Uysal NEwetz R(2021)An OCV-Aware Clock Tree Synthesis Methodology2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643585(1-9)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643585
Tan CEwetz RKoh CShin Y(2018)Clustering of flip-flops for useful-skew clock tree synthesisProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201728(507-512)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201728
Show More Cited By

Index Terms

Clock Tree Construction based on Arrival Time Constraints
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Clock-network synthesis

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cover image ACM Conferences

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

March 2017

176 pages

ISBN:9781450346962

DOI:10.1145/3036669

General Chair:
Mustafa Ozdal
Bilkent University
,
Program Chair:
Chris Chu
Iowa State University

Copyright © 2017 ACM.

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 March 2017

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National Science Foundation

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ISPD '17: International Symposium on Physical Design

March 19 - 22, 2017

Oregon, Portland, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Vanna-Iampikul PLu YShim DLim S(2023)GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICsACM Transactions on Design Automation of Electronic Systems10.1145/358857028:5(1-26)Online publication date: 6-Apr-2023
https://dl.acm.org/doi/10.1145/3588570
Uysal NEwetz R(2021)An OCV-Aware Clock Tree Synthesis Methodology2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643585(1-9)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643585
Tan CEwetz RKoh CShin Y(2018)Clustering of flip-flops for useful-skew clock tree synthesisProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201728(507-512)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201728
Tan CEwetz RKoh C(2018)Clustering of flip-flops for useful-skew clock tree synthesis2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297374(507-512)Online publication date: Jan-2018
https://doi.org/10.1109/ASPDAC.2018.8297374

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