research-article

Public Access

Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction

Authors:

Ankur SrivastavaAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 9, Pages 1 - 6

https://doi.org/10.1145/3061639.3062226

Published: 18 June 2017 Publication History

Abstract

Logic locking is a technique that has been proposed to thwart IC counterfeiting and overproduction by untrusted foundry. Recently, the security of logic locking is threatened by a new attack called SAT attack, which can effectively decipher the correct key of most logic locking techniques. In this paper, we propose a new technique called delay locking to enhance the security of existing logic locking techniques. For delay locking, the key into a locked circuit not only determines its functionality, but also its timing profile. A functionality-correct but timing-incorrect key will result in timing violations and thus making the circuit malfunction.

References

[1]

A. Baumgarten, A. Tyagi, and J. Zambreno. Preventing IC piracy using reconfigurable logic barriers. IEEE Design & Test of Computers, 2010.

Digital Library

[2]

C.-P. Chen, C. C. Chu, and D. Wong. Fast and exact simultaneous gate and wire sizing by lagrangian relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(7):1014--1025, 1999.

Digital Library

[3]

S. Dupuis, P.-S. Ba, G. Di Natale, M.-L. Flottes, and B. Rouzeyre. A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International, pages 49--54. IEEE, 2014.

[4]

V. Khandelwal and A. Srivastava. Variability-driven formulation for simultaneous gate sizing and postsilicon tunability allocation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008.

Digital Library

[5]

S. Kim, J. Kim, and S.-Y. Hwang. New path balancing algorithm for glitch power reduction. IEE Proceedings-Circuits, Devices and Systems, 148(3):151--156, 2001.

[6]

S. M. Plaza and I. L. Markov. Solving the third-shift problem in IC piracy with test-aware logic locking. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 34(6):961--971, 2015.

[7]

J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. Security analysis of logic obfuscation. In Proceedings of the 49th Annual Design Automation Conference, pages 83--89. ACM, 2012.

Digital Library

[8]

J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri. Fault analysis-based logic encryption. Computers, IEEE Transactions on, 64(2):410--424, 2015.

[9]

J. A. Roy, F. Koushanfar, and I. L. Markov. Epic: Ending piracy of integrated circuits. In Proceedings of the conference on Design, Automation and Test in Europe, pages 1069--1074. ACM, 2008.

Digital Library

[10]

P. Subramanyan, S. Ray, and S. Malik. Evaluating the security of logic encryption algorithms. In Hardware Oriented Security and Trust (HOST), 2015 IEEE International Symposium on, pages 137--143. IEEE, 2015.

[11]

J.-L. Tsai, D. Baik, C. C.-P. Chen, and K. K. Saluja. A yield improvement methodology using pre-and post-silicon statistical clock scheduling. In Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, pages 611--618. IEEE Computer Society, 2004.

Digital Library

[12]

Y. Xie and A. Srivastava. Mitigating sat attack on logic locking. Cryptographic Hardware and Embedded Systems (CHES), 2016.

[13]

M. Yasin, B. Mazumdar, J. J. Rajendran, and O. Sinanoglu. Sarlock: Sat attack resistant logic locking. In Hardware Oriented Security and Trust (HOST), 2016 IEEE International Symposium on, pages 236--241. IEEE, 2016.

[14]

M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. Security analysis of anti-sat. Cryptology ePrint Archive, Report 2016/896, 2016. http://eprint.iacr.org/2016/896.

[15]

M. Yasin, J. Rajendran, O. Sinanoglu, and R. Karri. On improving the security of logic locking. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2015.

Cited By

Mahfuz TBhunia SChakraborty P(2025)X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space ExplorationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.351585520(753-766)Online publication date: 2025
https://doi.org/10.1109/TIFS.2024.3515855
Abideen ZPagliarini SAbideen ZPagliarini S(2025)ReBO-Driven IC Design: Leveraging Reconfigurable Logic for ObfuscationReconfigurable Obfuscation Techniques for the IC Supply Chain10.1007/978-3-031-77509-3_3(43-56)Online publication date: 12-Jan-2025
https://doi.org/10.1007/978-3-031-77509-3_3
Wang ZXiong DHuang K(2024)Structural analysis attack on asynchronous obfuscated circuitsIEICE Electronics Express10.1587/elex.21.2024010721:11(20240107-20240107)Online publication date: 10-Jun-2024
https://doi.org/10.1587/elex.21.20240107
Show More Cited By

Recommendations

Pre-analysis locking: a safe and deadlock free locking policy
VLDB '85: Proceedings of the 11th international conference on Very Large Data Bases - Volume 11

A safe and deadlock free lock policy is introduced, called pre-analysis locking. Pre-analysis locking is based on an efficient geometric algorithm which inserts lock and unlock operations into the transactions. Pre-analysis locking is the first safe and ...
Locking Timestamps versus Locking Objects
PODC '18: Proceedings of the 2018 ACM Symposium on Principles of Distributed Computing

We present multiversion timestamp locking (MVTL), a new genre of multiversion concurrency control algorithms for serializable transactions. The key idea behind MVTL is simple: lock individual timestamps instead of locking objects. After presenting a ...
Altruistic locking

Long-lived transactions (LLTs) hold on to database resources for relatively long periods of time, significantly delaying the completion of shorter and more common transactions. To alleviate this problem we propose an extension to two-phase locking, ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 June 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article
Research
Refereed limited

Funding Sources

Conference

DAC '17

Sponsor:

EDAC
SIGDA

DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

87
Total Citations
View Citations
910
Total Downloads

Downloads (Last 12 months)140
Downloads (Last 6 weeks)38

Reflects downloads up to 18 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Mahfuz TBhunia SChakraborty P(2025)X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space ExplorationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.351585520(753-766)Online publication date: 2025
https://doi.org/10.1109/TIFS.2024.3515855
Abideen ZPagliarini SAbideen ZPagliarini S(2025)ReBO-Driven IC Design: Leveraging Reconfigurable Logic for ObfuscationReconfigurable Obfuscation Techniques for the IC Supply Chain10.1007/978-3-031-77509-3_3(43-56)Online publication date: 12-Jan-2025
https://doi.org/10.1007/978-3-031-77509-3_3
Wang ZXiong DHuang K(2024)Structural analysis attack on asynchronous obfuscated circuitsIEICE Electronics Express10.1587/elex.21.2024010721:11(20240107-20240107)Online publication date: 10-Jun-2024
https://doi.org/10.1587/elex.21.20240107
Hashemi MMohammadi SCarlson T(2024)SRLL: Improving Security and Reliability with User-Defined Constraint-Aware Logic LockingACM Journal on Emerging Technologies in Computing Systems10.1145/370913921:1(1-27)Online publication date: 23-Dec-2024
https://dl.acm.org/doi/10.1145/3709139
McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Wang JChen ZZhang JXu YYu TZheng ZYe EGeorge SYang HLiu YNi KNarayanan VLi X(2024)A Module-Level Configuration Methodology for Programmable Camouflaged LogicACM Transactions on Design Automation of Electronic Systems10.1145/364046229:2(1-31)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3640462
Talukdar JPaik WOrtega EChakrabarty K(2024)ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse EngineeringIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.341103332:8(1535-1548)Online publication date: Aug-2024
https://doi.org/10.1109/TVLSI.2024.3411033
Azar KKamali HFarahmandi FTehranipoor M(2024)Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An ExplorationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.335728619(2771-2785)Online publication date: 2024
https://doi.org/10.1109/TIFS.2024.3357286
Gubbi KLatibari BChowdhury MJalilzadeh AHamedani ERafatirad SSasan AHomayoun HSalehi S(2024)Optimized and Automated Secure IC Design Flow: A Defense-in-Depth ApproachIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.336416071:5(2031-2044)Online publication date: May-2024
https://doi.org/10.1109/TCSI.2024.3364160
Chakraborty PCruz JAlmawzan RMahfuz TBhunia S(2024)Learning Your Lock: Exploiting Structural Vulnerabilities in Logic LockingIEEE Design & Test10.1109/MDAT.2024.335456941:2(7-14)Online publication date: Apr-2024
https://doi.org/10.1109/MDAT.2024.3354569
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Figures

Tables

Media

View Table of Conten