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Developing an architecture validation suite: application to the PowerPC architecture

Authors:

Laurent Fournier,

Anatoly Koyfman,

Moshe LevingerAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 189 - 194

https://doi.org/10.1145/309847.309911

Published: 01 June 1999 Publication History

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Cited By

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Nanda MRajshekhar Rao P(2019)Increasing the Verification Analysis Using Tool Assessment as Per DO-25410.1007/978-981-13-3765-9_40(387-394)Online publication date: 8-Feb-2019
https://doi.org/10.1007/978-981-13-3765-9_40
Gray KKerneis GMulligan DPulte CSarkar SSewell PPrvulovic M(2015)An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessorsProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830775(635-646)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2830772.2830775
Sen A(2009)Mutation Operators for Concurrent SystemC DesignsProceedings of the 2009 10th International Workshop on Microprocessor Test and Verification10.1109/MTV.2009.8(27-31)Online publication date: 7-Dec-2009
https://dl.acm.org/doi/10.1109/MTV.2009.8
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Index Terms

Developing an architecture validation suite: application to the PowerPC architecture
1. Computer systems organization
  1. Architectures
    1. Other architectures

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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1999

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DAC99

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EDAC
SIGDA
IEEE-CAS

DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Nanda MRajshekhar Rao P(2019)Increasing the Verification Analysis Using Tool Assessment as Per DO-25410.1007/978-981-13-3765-9_40(387-394)Online publication date: 8-Feb-2019
https://doi.org/10.1007/978-981-13-3765-9_40
Gray KKerneis GMulligan DPulte CSarkar SSewell PPrvulovic M(2015)An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessorsProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830775(635-646)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2830772.2830775
Sen A(2009)Mutation Operators for Concurrent SystemC DesignsProceedings of the 2009 10th International Workshop on Microprocessor Test and Verification10.1109/MTV.2009.8(27-31)Online publication date: 7-Dec-2009
https://dl.acm.org/doi/10.1109/MTV.2009.8
Adir AAsaf SFournier LJaeger IPeled OLevitan S(2007)A framework for the validation of processor architecture complianceProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278702(902-905)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278702
Gluska AGetreu IFix LLavagno L(2003)Coverage-oriented verification of baniasProceedings of the 40th annual Design Automation Conference10.1145/775832.775906(280-285)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775906
Philipps JPretschner ASlotosch OAiglstorfer EKriebel SScholl K(2003)Model-Based Test Case Generation for Smart Cards1 1Support by the BMBF (project EMPRESS) is gratefully acknowledged.Electronic Notes in Theoretical Computer Science10.1016/S1571-0661(04)80817-X80(170-184)Online publication date: Aug-2003
https://doi.org/10.1016/S1571-0661(04)80817-X
Bhattacharyya NWang A(2001)Automatic test generation for micro-architectural verification of configurable microprocessor cores with user extensionsSixth IEEE International High-Level Design Validation and Test Workshop10.1109/HLDVT.2001.972801(14-15)Online publication date: 2001
https://doi.org/10.1109/HLDVT.2001.972801
Tasiran SKeutzer K(2001)Coverage Metrics for Functional Validation of Hardware DesignsIEEE Design & Test10.1109/54.93624718:4(36-45)Online publication date: 1-Jul-2001
https://dl.acm.org/doi/10.1109/54.936247
Puig-Medina MEzer GKonas PDe Micheli G(2000)Verification of configurable processor coresProceedings of the 37th Annual Design Automation Conference10.1145/337292.337527(426-431)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337527

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